Remove, or (where it might later come in handy) comment out artefacts
for 256 bit (AVX) code generation on amd64. Although that was the
plan at first, it turns out to be infeasible to generate 256 bit
instructions for the IR created by Memcheck's instrumentation of 256
bit Ity_V256 IR. This is because it would require 256 bit integer
SIMD operations, and AVX as currently available only provides 256 bit
operations for floating point. So, fall back to generating 256 IR
into 128-bit XMM register pairs, and using the existing SSE facilities
in the back end. This change only affects the amd64 back end -- it
does not affect IR, which remains unchanged, and capable of
representing 256 bit vector operations wherever needed.
git-svn-id: svn://svn.valgrind.org/vex/trunk@2355 8f6e269a-dfd6-0310-a8e1-e2731360e62c
6 files changed