commit 415a7b163803d1add7f58e03908ab7d46159970d
author tom <tom@a5019735-40e9-0310-863c-91ae7b9d1cf9> Fri Jan 02 11:03:55 2009 +0000
committer tom <tom@a5019735-40e9-0310-863c-91ae7b9d1cf9> Fri Jan 02 11:03:55 2009 +0000
tree e927b810d1c98c9f6a122036eb02dbc1d11fbd6d
parent 70c5e5a3487ae99fa65ddec85ef645e360838835

Remove spurious newlines from messages.


git-svn-id: svn://svn.valgrind.org/valgrind/trunk@8890 a5019735-40e9-0310-863c-91ae7b9d1cf9

cachegrind/cg-amd64.c

diff --git a/cachegrind/cg-amd64.c b/cachegrind/cg-amd64.c
index 42dbc55..9415875 100644
--- a/cachegrind/cg-amd64.c
+++ b/cachegrind/cg-amd64.c
@@ -144,21 +144,21 @@
       case 0x48:
          /* Real L2 cache configuration is:
             *L2c = (cache_t) { 3072, 12, 64 }; L2_found = True; */
-         VG_(message)(Vg_DebugMsg, "warning: 3Mb L2 cache detected, treating as 2Mb\n");
+         VG_(message)(Vg_DebugMsg, "warning: 3Mb L2 cache detected, treating as 2Mb");
          *L2c = (cache_t) { 2048, 8, 64 }; L2_found = True;
          break;
       case 0x49:
 	  if ((family == 15) && (model == 6))
 	      /* On Xeon MP (family F, model 6), this is for L3 */
 	      VG_(message)(Vg_DebugMsg, 
-			   "warning: L3 cache detected but ignored\n");
+			   "warning: L3 cache detected but ignored");
 	  else
 	      *L2c = (cache_t) { 4096, 16, 64 }; L2_found = True;
 	  break;
       case 0x4e:
          /* Real L2 cache configuration is:
             *L2c = (cache_t) { 6144, 24, 64 }; L2_found = True; */
-         VG_(message)(Vg_DebugMsg, "warning: 6Mb L2 cache detected, treating as 4Mb\n");
+         VG_(message)(Vg_DebugMsg, "warning: 6Mb L2 cache detected, treating as 4Mb");
          *L2c = (cache_t) { 4096, 16, 64 }; L2_found = True;
          break;
 
@@ -304,7 +304,7 @@
    vendor_id[12] = '\0';
 
    if (0 == level) {
-      VG_(message)(Vg_DebugMsg, "CPUID level is 0, early Pentium?\n");
+      VG_(message)(Vg_DebugMsg, "CPUID level is 0, early Pentium?");
       return -1;
    }
 

cachegrind/cg-x86.c

diff --git a/cachegrind/cg-x86.c b/cachegrind/cg-x86.c
index 0fe0489..7480dd5 100644
--- a/cachegrind/cg-x86.c
+++ b/cachegrind/cg-x86.c
@@ -144,21 +144,21 @@
       case 0x48:
          /* Real L2 cache configuration is:
             *L2c = (cache_t) { 3072, 12, 64 }; L2_found = True; */
-         VG_(message)(Vg_DebugMsg, "warning: 3Mb L2 cache detected, treating as 2Mb\n");
+         VG_(message)(Vg_DebugMsg, "warning: 3Mb L2 cache detected, treating as 2Mb");
          *L2c = (cache_t) { 2048, 8, 64 }; L2_found = True;
          break;
       case 0x49:
 	  if ((family == 15) && (model == 6))
 	      /* On Xeon MP (family F, model 6), this is for L3 */
 	      VG_(message)(Vg_DebugMsg, 
-			   "warning: L3 cache detected but ignored\n");
+			   "warning: L3 cache detected but ignored");
 	  else
 	      *L2c = (cache_t) { 4096, 16, 64 }; L2_found = True;
 	  break;
       case 0x4e:
          /* Real L2 cache configuration is:
             *L2c = (cache_t) { 6144, 24, 64 }; L2_found = True; */
-         VG_(message)(Vg_DebugMsg, "warning: 6Mb L2 cache detected, treating as 4Mb\n");
+         VG_(message)(Vg_DebugMsg, "warning: 6Mb L2 cache detected, treating as 4Mb");
          *L2c = (cache_t) { 4096, 16, 64 }; L2_found = True;
          break;
 
@@ -304,7 +304,7 @@
    vendor_id[12] = '\0';
 
    if (0 == level) {
-      VG_(message)(Vg_DebugMsg, "CPUID level is 0, early Pentium?\n");
+      VG_(message)(Vg_DebugMsg, "CPUID level is 0, early Pentium?");
       return -1;
    }