commit 4970e4e219cb92ef15de742d102c537ea33d5430
author sewardj <sewardj@8f6e269a-dfd6-0310-a8e1-e2731360e62c> Sat Oct 11 10:07:55 2008 +0000
committer sewardj <sewardj@8f6e269a-dfd6-0310-a8e1-e2731360e62c> Sat Oct 11 10:07:55 2008 +0000
tree 1750fca227a98766811c72e5b55d89e581eed8e3
parent a203330aad67bc3e52ca1395a55e94ef9a091223

Support FPREM1 on amd64.  Fixes #172563.


git-svn-id: svn://svn.valgrind.org/vex/trunk@1865 8f6e269a-dfd6-0310-a8e1-e2731360e62c

priv/host-amd64/isel.c

diff --git a/priv/host-amd64/isel.c b/priv/host-amd64/isel.c
index 26af493..88777b8 100644
--- a/priv/host-amd64/isel.c
+++ b/priv/host-amd64/isel.c
@@ -1761,7 +1761,8 @@
    case Iex_Triop: {
       /* C3210 flags following FPU partial remainder (fprem), both
          IEEE compliant (PREM1) and non-IEEE compliant (PREM). */
-      if (e->Iex.Triop.op == Iop_PRemC3210F64) {
+      if (e->Iex.Triop.op == Iop_PRemC3210F64
+          || e->Iex.Triop.op == Iop_PRem1C3210F64) {
          AMD64AMode* m8_rsp = AMD64AMode_IR(-8, hregAMD64_RSP());
          HReg        arg1   = iselDblExpr(env, e->Iex.Triop.arg2);
          HReg        arg2   = iselDblExpr(env, e->Iex.Triop.arg3);
@@ -1780,6 +1781,9 @@
             case Iop_PRemC3210F64:
                addInstr(env, AMD64Instr_A87FpOp(Afp_PREM));
                break;
+            case Iop_PRem1C3210F64:
+               addInstr(env, AMD64Instr_A87FpOp(Afp_PREM1));
+               break;
             default: 
                vassert(0);
          }
@@ -2936,14 +2940,16 @@
            || e->Iex.Triop.op == Iop_AtanF64
            || e->Iex.Triop.op == Iop_Yl2xF64
            || e->Iex.Triop.op == Iop_Yl2xp1F64
-           || e->Iex.Triop.op == Iop_PRemF64)
+           || e->Iex.Triop.op == Iop_PRemF64
+           || e->Iex.Triop.op == Iop_PRem1F64)
       ) {
       AMD64AMode* m8_rsp = AMD64AMode_IR(-8, hregAMD64_RSP());
       HReg        arg1   = iselDblExpr(env, e->Iex.Triop.arg2);
       HReg        arg2   = iselDblExpr(env, e->Iex.Triop.arg3);
       HReg        dst    = newVRegV(env);
       Bool     arg2first = toBool(e->Iex.Triop.op == Iop_ScaleF64 
-                                  || e->Iex.Triop.op == Iop_PRemF64);
+                                  || e->Iex.Triop.op == Iop_PRemF64
+                                  || e->Iex.Triop.op == Iop_PRem1F64);
       addInstr(env, AMD64Instr_A87Free(2));
 
       /* one arg -> top of x87 stack */
@@ -2975,6 +2981,9 @@
          case Iop_PRemF64:
             addInstr(env, AMD64Instr_A87FpOp(Afp_PREM));
             break;
+         case Iop_PRem1F64:
+            addInstr(env, AMD64Instr_A87FpOp(Afp_PREM1));
+            break;
          default: 
             vassert(0);
       }