Rename the SSE and MMX uinstrs which read/write integer registers, in
a way consistent with the position of the register field in the
instruction. In Intel encoding parlance, the G register is in bits
5,4,3 and the E register is bits 2,1,0, and so we adopt this scheme
consistently. Considering how much confusion this has caused me in
this recent bout of SSE hacking, consistent renaming can only be a
good thing. It makes it a lot easier to figure out if parts of the
SSE handling machinery are correct, or not.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@1698 a5019735-40e9-0310-863c-91ae7b9d1cf9
diff --git a/addrcheck/ac_main.c b/addrcheck/ac_main.c
index 407d001..cec7186 100644
--- a/addrcheck/ac_main.c
+++ b/addrcheck/ac_main.c
@@ -1013,7 +1013,7 @@
// case SSE2a1_MemRd:
// case SSE2a1_MemWr:
- case SSE3g1_RegRd:
+ case SSE3e1_RegRd:
// case SSE3a1_MemRd:
// case SSE3a1_MemWr:
VG_(pp_UInstr)(0,u_in);
@@ -1023,7 +1023,7 @@
case SSE3g1_RegWr:
case SSE5:
case SSE3g_RegWr:
- case SSE3g_RegRd:
+ case SSE3e_RegRd:
case SSE4:
default:
VG_(copy_UInstr)(cb, u_in);