diff --git a/addrcheck/ac_main.c b/addrcheck/ac_main.c
index 407d001..cec7186 100644
--- a/addrcheck/ac_main.c
+++ b/addrcheck/ac_main.c
@@ -1013,7 +1013,7 @@
 
 	    //         case SSE2a1_MemRd:
 	    //         case SSE2a1_MemWr:
-         case SSE3g1_RegRd:
+         case SSE3e1_RegRd:
 	   //         case SSE3a1_MemRd:
 	   //         case SSE3a1_MemWr:
 	    VG_(pp_UInstr)(0,u_in);
@@ -1023,7 +1023,7 @@
          case SSE3g1_RegWr:
          case SSE5:
          case SSE3g_RegWr:
-         case SSE3g_RegRd:
+         case SSE3e_RegRd:
          case SSE4:
          default:
             VG_(copy_UInstr)(cb, u_in);
diff --git a/coregrind/vg_from_ucode.c b/coregrind/vg_from_ucode.c
index 8b699e6..9bf4332 100644
--- a/coregrind/vg_from_ucode.c
+++ b/coregrind/vg_from_ucode.c
@@ -3744,7 +3744,7 @@
                              u->val2 );
          break;
 
-      case MMX2_RegRd:
+      case MMX2_ERegRd:
          vg_assert(u->tag1 == Lit16);
          vg_assert(u->tag2 == RealReg);
          vg_assert(u->tag3 == NoValue);
@@ -3759,7 +3759,7 @@
                                     u->val2 );
          break;
 
-      case MMX2_RegWr:
+      case MMX2_ERegWr:
          vg_assert(u->tag1 == Lit16);
          vg_assert(u->tag2 == RealReg);
          vg_assert(u->tag3 == NoValue);
@@ -3849,7 +3849,7 @@
                       u->val3 );
          break;
 
-      case SSE3g_RegRd:
+      case SSE3e_RegRd:
       case SSE3g_RegWr:
          vg_assert(u->size == 4);
          vg_assert(u->tag1 == Lit16);
@@ -3860,7 +3860,7 @@
             emit_get_sse_state();
             *sselive = True;
          }
-	 if (u->opcode==SSE3g_RegRd) {
+	 if (u->opcode==SSE3e_RegRd) {
             emit_SSE3g_RegRd ( u->flags_r, u->flags_w,
                                (u->val1 >> 8) & 0xFF,
                                u->val1 & 0xFF,
@@ -3896,7 +3896,7 @@
                              u->val3 );
          break;
 
-      case SSE3g1_RegRd:
+      case SSE3e1_RegRd:
          vg_assert(u->size == 2);
          vg_assert(u->tag1 == Lit16);
          vg_assert(u->tag2 == Lit16);
diff --git a/coregrind/vg_to_ucode.c b/coregrind/vg_to_ucode.c
index 10d8653..e622bf7 100644
--- a/coregrind/vg_to_ucode.c
+++ b/coregrind/vg_to_ucode.c
@@ -3729,7 +3729,7 @@
       if (epartIsReg(modrm)) { 
          uInstr2(cb, GET, 4, ArchReg, eregOfRM(modrm), TempReg, t1);
          vg_assert(epartIsReg(modrm));
-         uInstr3(cb, SSE3g_RegRd, 4,
+         uInstr3(cb, SSE3e_RegRd, 4,
                      Lit16, (((UShort)insn[0]) << 8) | (UShort)insn[1],
                      Lit16, (((UShort)insn[2]) << 8) | (UShort)modrm,
                      TempReg, t1 );
@@ -4214,7 +4214,7 @@
       if (epartIsReg(modrm) && !is_store) {
          t1 = newTemp(cb);
 	 uInstr2(cb, GET, 4, ArchReg, eregOfRM(modrm), TempReg, t1);
-         uInstr3(cb, SSE3g_RegRd, 4,
+         uInstr3(cb, SSE3e_RegRd, 4,
                      Lit16, (((UShort)0x66) << 8) | (UShort)insn[0],
                      Lit16, (((UShort)insn[1]) << 8) | (UShort)modrm,
                      TempReg, t1 );
@@ -4257,7 +4257,7 @@
       if (epartIsReg(modrm)) {
          uInstr2(cb, GET, 2, ArchReg, eregOfRM(modrm), TempReg, t1);
          vg_assert(epartIsReg(modrm));
-         uInstr3(cb, SSE3g1_RegRd, 2,
+         uInstr3(cb, SSE3e1_RegRd, 2,
                      Lit16, (((UShort)0x66) << 8) | (UShort)insn[0],
                      Lit16, (((UShort)insn[1]) << 8) | (UShort)modrm,
                      TempReg, t1 );
@@ -5811,7 +5811,7 @@
          if (epartIsReg(modrm)) {
             eip++;
             t1 = newTemp(cb);
-            uInstr2(cb, MMX2_RegWr, 4, 
+            uInstr2(cb, MMX2_ERegWr, 4, 
                         Lit16, 
                         (((UShort)(opc)) << 8) | ((UShort)modrm),
                         TempReg, t1 );
@@ -5843,7 +5843,7 @@
             eip++;
             t1 = newTemp(cb);
             uInstr2(cb, GET, 4, ArchReg, eregOfRM(modrm), TempReg, t1);
-            uInstr2(cb, MMX2_RegRd, 4, 
+            uInstr2(cb, MMX2_ERegRd, 4, 
                         Lit16, 
                         (((UShort)(opc)) << 8) | ((UShort)modrm),
                         TempReg, t1 );
diff --git a/coregrind/vg_translate.c b/coregrind/vg_translate.c
index 7f9570b..5a5dfd4 100644
--- a/coregrind/vg_translate.c
+++ b/coregrind/vg_translate.c
@@ -551,22 +551,22 @@
                        u->regparms_n <= u->argc && XCCALL;
    /* Fields checked:     lit32   size  flags_r/w tag1   tag2   tag3    (rest) */
    case MMX1:
-   case MMX2:       return LIT0 && SZ0  && CC0 &&  Ls1 &&  N2 &&  N3 && XOTHER;
-   case MMX3:       return LIT0 && SZ0  && CC0 &&  Ls1 && Ls2 &&  N3 && XOTHER;
-   case MMX2_MemRd: return LIT0 && SZ48 && CC0 &&  Ls1 && TR2 &&  N3 && XOTHER;
-   case MMX2_MemWr: return LIT0 && SZ48 && CC0 &&  Ls1 && TR2 &&  N3 && XOTHER;
-   case MMX2_RegRd: return LIT0 && SZ4  && CC0 &&  Ls1 && TR2 &&  N3 && XOTHER;
-   case MMX2_RegWr: return LIT0 && SZ4  && CC0 &&  Ls1 && TR2 &&  N3 && XOTHER;
+   case MMX2:        return LIT0 && SZ0  && CC0 &&  Ls1 &&  N2 &&  N3 && XOTHER;
+   case MMX3:        return LIT0 && SZ0  && CC0 &&  Ls1 && Ls2 &&  N3 && XOTHER;
+   case MMX2_MemRd:  return LIT0 && SZ48 && CC0 &&  Ls1 && TR2 &&  N3 && XOTHER;
+   case MMX2_MemWr:  return LIT0 && SZ48 && CC0 &&  Ls1 && TR2 &&  N3 && XOTHER;
+   case MMX2_ERegRd: return LIT0 && SZ4  && CC0 &&  Ls1 && TR2 &&  N3 && XOTHER;
+   case MMX2_ERegWr: return LIT0 && SZ4  && CC0 &&  Ls1 && TR2 &&  N3 && XOTHER;
 
    /* Fields checked:        lit32   size  flags_r/w tag1   tag2   tag3    (rest) */
    case SSE2a_MemWr:  return LIT0 && SZ416 && CC0  && Ls1 && Ls2 && TR3 && XOTHER;
    case SSE2a_MemRd:  return LIT0 && SZ416 && CC0  && Ls1 && Ls2 && TR3 && XOTHER;
    case SSE3a_MemWr:  return LIT0 && SZsse && CC0  && Ls1 && Ls2 && TR3 && XOTHER;
    case SSE3a_MemRd:  return LIT0 && SZsse && CCf  && Ls1 && Ls2 && TR3 && XOTHER;
-   case SSE3g_RegRd:  return LIT0 && SZ4   && CC0  && Ls1 && Ls2 && TR3 && XOTHER;
+   case SSE3e_RegRd:  return LIT0 && SZ4   && CC0  && Ls1 && Ls2 && TR3 && XOTHER;
    case SSE3g_RegWr:  return LIT0 && SZ4   && CC0  && Ls1 && Ls2 && TR3 && XOTHER;
    case SSE3g1_RegWr: return LIT8 && SZ4   && CC0  && Ls1 && Ls2 && TR3 && XOTHER;
-   case SSE3g1_RegRd: return LIT8 && SZ2   && CC0  && Ls1 && Ls2 && TR3 && XOTHER;
+   case SSE3e1_RegRd: return LIT8 && SZ2   && CC0  && Ls1 && Ls2 && TR3 && XOTHER;
    case SSE3:         return LIT0 && SZ0   && CC0  && Ls1 && Ls2 && N3  && XOTHER;
    case SSE4:         return LIT0 && SZ0   && CCf  && Ls1 && Ls2 && N3  && XOTHER;
    case SSE5:         return LIT0 && SZ0   && CC0  && Ls1 && Ls2 && Ls3 && XOTHER;
@@ -882,14 +882,14 @@
       case MMX3:       return "MMX3" ;
       case MMX2_MemRd: return "MMX2_MRd" ;
       case MMX2_MemWr: return "MMX2_MWr" ;
-      case MMX2_RegRd: return "MMX2_RRd" ;
-      case MMX2_RegWr: return "MMX2_RWr" ;
+      case MMX2_ERegRd: return "MMX2_eRRd" ;
+      case MMX2_ERegWr: return "MMX2_eRWr" ;
       case SSE2a_MemWr: return "SSE2a_MWr";
       case SSE2a_MemRd: return "SSE2a_MRd";
-      case SSE3g_RegRd: return "SSE3g_RRd";
+      case SSE3e_RegRd: return "SSE3e_RRd";
       case SSE3g_RegWr: return "SSE3g_RWr";
       case SSE3g1_RegWr: return "SSE3g1_RWr";
-      case SSE3g1_RegRd: return "SSE3g1_RRd";
+      case SSE3e1_RegRd: return "SSE3e1_RRd";
       case SSE3:        return "SSE3";
       case SSE4:        return "SSE4";
       case SSE5:        return "SSE5";
@@ -1032,8 +1032,8 @@
                      (u->val1 >> 8) & 0xFF, u->val1 & 0xFF, u->val2 & 0xFF );
          break;
 
-      case MMX2_RegWr:
-      case MMX2_RegRd:
+      case MMX2_ERegWr:
+      case MMX2_ERegRd:
          VG_(printf)("0x%x:0x%x, ",
                      (u->val1 >> 8) & 0xFF, u->val1 & 0xFF );
          VG_(pp_UOperand)(u, 2, 4, False);
@@ -1061,7 +1061,7 @@
          VG_(pp_UOperand)(u, 3, 4, True);
          break;
 
-      case SSE3g_RegRd:
+      case SSE3e_RegRd:
       case SSE3g_RegWr:
          VG_(printf)("0x%x:0x%x:0x%x:0x%x",
                      (u->val1 >> 8) & 0xFF, u->val1 & 0xFF, 
@@ -1070,7 +1070,7 @@
          break;
 
       case SSE3g1_RegWr:
-      case SSE3g1_RegRd:
+      case SSE3e1_RegRd:
          VG_(printf)("0x%x:0x%x:0x%x:0x%x:0x%x",
                      (u->val1 >> 8) & 0xFF, u->val1 & 0xFF, 
                      (u->val2 >> 8) & 0xFF, u->val2 & 0xFF,
@@ -1250,11 +1250,11 @@
       case LEA1: RD(1); WR(2); break;
       case LEA2: RD(1); RD(2); WR(3); break;
 
-      case SSE3g_RegRd:
+      case SSE3e_RegRd:
       case SSE3a_MemWr:
       case SSE3a_MemRd:
       case SSE2a_MemWr: 
-      case SSE3g1_RegRd:
+      case SSE3e1_RegRd:
       case SSE2a_MemRd: RD(3); break;
 
       case SSE3g1_RegWr:
@@ -1262,8 +1262,8 @@
 
       case SSE3ag_MemRd_RegWr: RD(1); WR(2); break;
 
-      case MMX2_RegRd: RD(2); break;
-      case MMX2_RegWr: WR(2); break;
+      case MMX2_ERegRd: RD(2); break;
+      case MMX2_ERegWr: WR(2); break;
 
       case SSE4: case SSE3: case SSE5:
       case MMX1: case MMX2: case MMX3:
@@ -1416,11 +1416,11 @@
       case FPU: case FPU_R: case FPU_W:
       case MMX1: case MMX2: case MMX3:
       case MMX2_MemRd: case MMX2_MemWr:
-      case MMX2_RegRd: case MMX2_RegWr:
+      case MMX2_ERegRd: case MMX2_ERegWr:
       case SSE2a_MemWr: case SSE2a_MemRd:
       case SSE3a_MemWr: case SSE3a_MemRd:
-      case SSE3g_RegRd: case SSE3g_RegWr: 
-      case SSE3g1_RegWr: case SSE3g1_RegRd:
+      case SSE3e_RegRd: case SSE3g_RegWr: 
+      case SSE3g1_RegWr: case SSE3e1_RegRd:
       case SSE4: case SSE3: case SSE5: case SSE3ag_MemRd_RegWr:
       case WIDEN:
       /* GETSEG and USESEG are to do with ArchRegS, not ArchReg */
diff --git a/helgrind/hg_main.c b/helgrind/hg_main.c
index e016f17..f29b980 100644
--- a/helgrind/hg_main.c
+++ b/helgrind/hg_main.c
@@ -2203,7 +2203,7 @@
 
          case MMX1: case MMX2: case MMX3:
          case MMX2_MemRd: case MMX2_MemWr:
-         case MMX2_RegRd: case MMX2_RegWr:
+         case MMX2_ERegRd: case MMX2_ERegWr:
             VG_(skin_panic)(
                "I don't know how to instrument MMXish stuff (yet)");
             break;
diff --git a/include/vg_skin.h b/include/vg_skin.h
index 6e37a98..1ac7767 100644
--- a/include/vg_skin.h
+++ b/include/vg_skin.h
@@ -565,14 +565,14 @@
       MMX2_MemRd,
       MMX2_MemWr,
 
-      /* 2 bytes, reads/writes an integer register.  Insns of the form
+      /* 2 bytes, reads/writes an integer ("E") register.  Insns of the form
          bbbbbbbb:11 mmxreg ireg.
          Held in val1[15:0], and ireg is to be replaced
          at codegen time by a reference to the relevant RealReg.
          Transfer is always at size 4.  Arg2 holds this Temp/Real Reg.
       */
-      MMX2_RegRd,
-      MMX2_RegWr,
+      MMX2_ERegRd,
+      MMX2_ERegWr,
 
       /* ------------ SSE/SSE2 ops ------------ */
       /* In the following:
@@ -584,13 +584,15 @@
          to be replaced at codegen time to a Temp/RealReg holding the
          address.
 
-         'g' indicates a byte of the form '11 xmmreg ireg', where ireg
-         is written, and is to be replaced at codegen time by a
-         reference to the relevant RealReg.
+         'e' indicates a byte of the form '11 xmmreg ireg', where ireg
+         is read or written, and is to be replaced at codegen time by
+         a reference to the relevant RealReg.  'e' because it's the E
+         reg in Intel encoding parlance.
 
-         'h' indicates a byte of the form '11 ireg xmmreg', where ireg
-         is read, and is to be replaced at codegen time by a reference
-         to the relevant RealReg.  */
+         'g' indicates a byte of the form '11 ireg xmmreg', where ireg
+         is read or written, and is to be replaced at codegen time by
+         a reference to the relevant RealReg.  'g' because it's called
+         G in Intel parlance. */
 
       /* 3 bytes, no memrefs, no iregdefs, copy exactly to the
          output.  Held in val1[15:0] and val2[7:0]. */
@@ -629,7 +631,7 @@
       SSE2a1_MemWr,
 #endif
       /* 4 bytes, writes an integer register.  Insns of the form
-         bbbbbbbb:bbbbbbbb:bbbbbbbb:11 ireg xmmreg.
+         bbbbbbbb:bbbbbbbb:bbbbbbbb:11 ireg bbb.
          Held in val1[15:0] and val2[15:0], and ireg is to be replaced
          at codegen time by a reference to the relevant RealReg.
          Transfer is always at size 4.  Arg3 holds this Temp/Real Reg.
@@ -645,6 +647,14 @@
       */
       SSE3g1_RegWr,
 
+      /* 4 bytes, reads an integer register.  Insns of the form
+         bbbbbbbb:bbbbbbbb:bbbbbbbb:11 bbb ireg.
+         Held in val1[15:0] and val2[15:0], and ireg is to be replaced
+         at codegen time by a reference to the relevant RealReg.
+         Transfer is always at size 4.  Arg3 holds this Temp/Real Reg.
+      */
+      SSE3e_RegRd,
+
       /* 5 bytes, reads an integer register.  Insns of the form
          bbbbbbbb:bbbbbbbb:bbbbbbbb: 11 bbb ireg :bbbbbbbb. Held in
          val1[15:0] and val2[15:0] and lit32[7:0], and ireg is to be
@@ -652,15 +662,7 @@
          RealReg.  Transfer is always at size 4.  Arg3 holds this
          Temp/Real Reg.
       */
-      SSE3g1_RegRd,
-
-      /* 4 bytes, reads an integer register.  Insns of the form
-         bbbbbbbb:bbbbbbbb:bbbbbbbb:11 xmmreg ireg.
-         Held in val1[15:0] and val2[15:0], and ireg is to be replaced
-         at codegen time by a reference to the relevant RealReg.
-         Transfer is always at size 4.  Arg3 holds this Temp/Real Reg.
-      */
-      SSE3g_RegRd,
+      SSE3e1_RegRd,
 
       /* 4 bytes, reads memory, writes an integer register, but is
          nevertheless an SSE insn.  The insn is of the form
diff --git a/lackey/lk_main.c b/lackey/lk_main.c
index a226922..a45453a 100644
--- a/lackey/lk_main.c
+++ b/lackey/lk_main.c
@@ -184,7 +184,7 @@
 
          case MMX1: case MMX2: case MMX3:
          case MMX2_MemRd: case MMX2_MemWr:
-         case MMX2_RegRd: case MMX2_RegWr:
+         case MMX2_ERegRd: case MMX2_ERegWr:
             VG_(skin_panic)(
                "I don't know how to instrument MMXish stuff (yet)");
             break;
diff --git a/memcheck/mc_translate.c b/memcheck/mc_translate.c
index da4969e..42eb478 100644
--- a/memcheck/mc_translate.c
+++ b/memcheck/mc_translate.c
@@ -1119,7 +1119,7 @@
          /* Since we don't track definedness of values inside the
             MMX state, we'd better check that the (int) reg being
             read here is defined. */
-         case MMX2_RegRd: 
+         case MMX2_ERegRd: 
             sk_assert(u_in->tag2 == TempReg);
             sk_assert(u_in->size == 4);
             uInstr1(cb, TESTV, 4, TempReg, SHADOW(u_in->val2));
@@ -1129,7 +1129,7 @@
 
 	 /* The MMX register is assumed to be fully defined, so
 	    that's what this register becomes. */
-         case MMX2_RegWr:
+         case MMX2_ERegWr:
             sk_assert(u_in->tag2 == TempReg);
             sk_assert(u_in->size == 4);
             uInstr1(cb, SETV,  4, TempReg, SHADOW(u_in->val2));