tree 66a131d8176d45b8b4c59e670510332944721d99
parent bc148f28ad2c0da095dd4e3ea9a21fbe41299b3a
author sewardj <sewardj@a5019735-40e9-0310-863c-91ae7b9d1cf9> 1055714074 +0000
committer sewardj <sewardj@a5019735-40e9-0310-863c-91ae7b9d1cf9> 1055714074 +0000

Rename the SSE and MMX uinstrs which read/write integer registers, in
a way consistent with the position of the register field in the
instruction.  In Intel encoding parlance, the G register is in bits
5,4,3 and the E register is bits 2,1,0, and so we adopt this scheme
consistently.  Considering how much confusion this has caused me in
this recent bout of SSE hacking, consistent renaming can only be a
good thing.  It makes it a lot easier to figure out if parts of the
SSE handling machinery are correct, or not.


git-svn-id: svn://svn.valgrind.org/valgrind/trunk@1698 a5019735-40e9-0310-863c-91ae7b9d1cf9