Change the way Vex represents architecture variants into something
more flexible. Prior to this change, the type VexSubArch effectively
imposed a total ordering on subarchitecture capabilities, which was
overly restrictive. This change moves to effectively using a bit-set,
allowing some features (instruction groups) to be supported or not
supported independently of each other.
git-svn-id: svn://svn.valgrind.org/vex/trunk@1555 8f6e269a-dfd6-0310-a8e1-e2731360e62c
diff --git a/priv/guest-amd64/toIR.c b/priv/guest-amd64/toIR.c
index 6dcee7b..ab3034c 100644
--- a/priv/guest-amd64/toIR.c
+++ b/priv/guest-amd64/toIR.c
@@ -13231,14 +13231,13 @@
HChar* fName = NULL;
void* fAddr = NULL;
if (haveF2orF3(pfx)) goto decode_failure;
- switch (archinfo->subarch) {
- case VexSubArch_NONE:
- fName = "amd64g_dirtyhelper_CPUID";
- fAddr = &amd64g_dirtyhelper_CPUID;
- break;
- default:
- vpanic("disInstr(amd64)(cpuid)");
+ if (archinfo->hwcaps == 0/*baseline, == SSE2*/) {
+ fName = "amd64g_dirtyhelper_CPUID";
+ fAddr = &amd64g_dirtyhelper_CPUID;
}
+ else
+ vpanic("disInstr(amd64)(cpuid)");
+
vassert(fName); vassert(fAddr);
d = unsafeIRDirty_0_N ( 0/*regparms*/,
fName, fAddr, mkIRExprVec_0() );