diff --git a/coregrind/m_machine.c b/coregrind/m_machine.c
index c09d528..ea05d2b 100644
--- a/coregrind/m_machine.c
+++ b/coregrind/m_machine.c
@@ -774,6 +774,7 @@
         have_mmxext = True;
 
      va = VexArchX86;
+     vai.endness = VexEndnessLE;
      if (have_sse2 && have_sse1 && have_mmxext) {
         vai.hwcaps  = VEX_HWCAPS_X86_MMXEXT;
         vai.hwcaps |= VEX_HWCAPS_X86_SSE1;
@@ -891,14 +892,15 @@
         have_avx2 = (ebx & (1<<5)) != 0; /* True => have AVX2 */
      }
 
-     va         = VexArchAMD64;
-     vai.hwcaps = (have_sse3   ? VEX_HWCAPS_AMD64_SSE3   : 0)
-                | (have_cx16   ? VEX_HWCAPS_AMD64_CX16   : 0)
-                | (have_lzcnt  ? VEX_HWCAPS_AMD64_LZCNT  : 0)
-                | (have_avx    ? VEX_HWCAPS_AMD64_AVX    : 0)
-                | (have_bmi    ? VEX_HWCAPS_AMD64_BMI    : 0)
-                | (have_avx2   ? VEX_HWCAPS_AMD64_AVX2   : 0)
-                | (have_rdtscp ? VEX_HWCAPS_AMD64_RDTSCP : 0);
+     va          = VexArchAMD64;
+     vai.endness = VexEndnessLE;
+     vai.hwcaps  = (have_sse3   ? VEX_HWCAPS_AMD64_SSE3   : 0)
+                 | (have_cx16   ? VEX_HWCAPS_AMD64_CX16   : 0)
+                 | (have_lzcnt  ? VEX_HWCAPS_AMD64_LZCNT  : 0)
+                 | (have_avx    ? VEX_HWCAPS_AMD64_AVX    : 0)
+                 | (have_bmi    ? VEX_HWCAPS_AMD64_BMI    : 0)
+                 | (have_avx2   ? VEX_HWCAPS_AMD64_AVX2   : 0)
+                 | (have_rdtscp ? VEX_HWCAPS_AMD64_RDTSCP : 0);
 
      VG_(machine_get_cache_info)(&vai);
 
@@ -1047,6 +1049,7 @@
      VG_(machine_ppc32_has_VMX) = have_V ? 1 : 0;
 
      va = VexArchPPC32;
+     vai.endness = VexEndnessBE;
 
      vai.hwcaps = 0;
      if (have_F)  vai.hwcaps |= VEX_HWCAPS_PPC32_F;
@@ -1185,6 +1188,9 @@
      VG_(machine_ppc64_has_VMX) = have_V ? 1 : 0;
 
      va = VexArchPPC64;
+     // CARLL fixme: when the time comes, copy .endness setting code
+     // from the VGA_mips32 case
+     vai.endness = VexEndnessBE;
 
      vai.hwcaps = 0;
      if (have_V)  vai.hwcaps |= VEX_HWCAPS_PPC64_V;
@@ -1277,6 +1283,7 @@
      r = VG_(sigprocmask)(VKI_SIG_SETMASK, &saved_set, NULL);
      vg_assert(r == 0);
      va = VexArchS390X;
+     vai.endness = VexEndnessBE;
 
      vai.hwcaps = model;
      if (have_STFLE) vai.hwcaps |= VEX_HWCAPS_S390X_STFLE;
@@ -1438,6 +1445,7 @@
      VG_(machine_arm_archlevel) = archlevel;
 
      va = VexArchARM;
+     vai.endness = VexEndnessLE;
 
      vai.hwcaps = VEX_ARM_ARCHLEVEL(archlevel);
      if (have_VFP3) vai.hwcaps |= VEX_HWCAPS_ARM_VFP3;
@@ -1453,6 +1461,7 @@
 #elif defined(VGA_arm64)
    {
      va = VexArchARM64;
+     vai.endness = VexEndnessLE;
 
      /* So far there are no variants. */
      vai.hwcaps = 0;
@@ -1486,6 +1495,14 @@
 
      vai.hwcaps = model;
 
+#    if defined(VKI_LITTLE_ENDIAN)
+     vai.endness = VexEndnessLE;
+#    elif defined(VKI_BIG_ENDIAN)
+     vai.endness = VexEndnessBE;
+#    else
+     vai.endness = VexEndness_INVALID;
+#    endif
+
      /* Same instruction set detection algorithm as for ppc32/arm... */
      vki_sigset_t          saved_set, tmp_set;
      vki_sigaction_fromK_t saved_sigill_act;
@@ -1565,11 +1582,19 @@
    {
      va = VexArchMIPS64;
      UInt model = VG_(get_machine_model)();
-     if (model== -1)
+     if (model == -1)
          return False;
 
      vai.hwcaps = model;
 
+#    if defined(VKI_LITTLE_ENDIAN)
+     vai.endness = VexEndnessLE;
+#    elif defined(VKI_BIG_ENDIAN)
+     vai.endness = VexEndnessBE;
+#    else
+     vai.endness = VexEndness_INVALID;
+#    endif
+
      VG_(machine_get_cache_info)(&vai);
 
      return True;