Add infrastructural support (IR, VEX) to allow returns of 128-
and 256-bit values from dirty helper functions, in a way which is
independent of the target ABIs and of compilers generating
correct struct return code.
Is a prereq for bug #294285.
MIPS fixes: Petar Jovanovic, mips32r2@gmail.com
S390 fixes: Maran, maranp@linux.vnet.ibm.com
git-svn-id: svn://svn.valgrind.org/vex/trunk@2739 8f6e269a-dfd6-0310-a8e1-e2731360e62c
diff --git a/priv/host_ppc_defs.c b/priv/host_ppc_defs.c
index 28dbac2..8d3c007 100644
--- a/priv/host_ppc_defs.c
+++ b/priv/host_ppc_defs.c
@@ -850,7 +850,7 @@
/* Only r3 .. r10 inclusive may be used as arg regs. Hence: */
mask = (1<<3)|(1<<4)|(1<<5)|(1<<6)|(1<<7)|(1<<8)|(1<<9)|(1<<10);
vassert(0 == (argiregs & ~mask));
- vassert(rloc != RetLocINVALID);
+ vassert(is_sane_RetLoc(rloc));
return i;
}
PPCInstr* PPCInstr_XDirect ( Addr64 dstGA, PPCAMode* amCIA,
@@ -3913,7 +3913,7 @@
case Pin_Call: {
if (i->Pin.Call.cond.test != Pct_ALWAYS
- && i->Pin.Call.rloc != RetLocNone) {
+ && i->Pin.Call.rloc.pri != RLPri_None) {
/* The call might not happen (it isn't unconditional) and it
returns a result. In this case we will need to generate a
control flow diamond to put 0x555..555 in the return