commit 7420b0969284c2e6d7421204d29b1bc2b1234ed6
author sewardj <sewardj@8f6e269a-dfd6-0310-a8e1-e2731360e62c> Sun Mar 13 20:19:19 2005 +0000
committer sewardj <sewardj@8f6e269a-dfd6-0310-a8e1-e2731360e62c> Sun Mar 13 20:19:19 2005 +0000
tree 19a3449b784e8470aa132936cc975fc829005491
parent 5a8334e7eb11f2d194f4c6ed9472027af21ab4eb

Fill in missing memory case for pinsrw.


git-svn-id: svn://svn.valgrind.org/vex/trunk@1029 8f6e269a-dfd6-0310-a8e1-e2731360e62c

priv/guest-x86/toIR.c

diff --git a/priv/guest-x86/toIR.c b/priv/guest-x86/toIR.c
index ad84d30..daf449f 100644
--- a/priv/guest-x86/toIR.c
+++ b/priv/guest-x86/toIR.c
@@ -7803,14 +7803,19 @@
 
       if (epartIsReg(modrm)) {
          assign(t4, getIReg(2, eregOfRM(modrm)));
-         lane = insn[3];
          delta += 2+2;
+         lane = insn[2+2-1];
          DIP("pinsrw $%d,%s,%s\n", (Int)lane, 
                                    nameIReg(2,eregOfRM(modrm)),
                                    nameMMXReg(gregOfRM(modrm)));
       } else {
-         /* awaiting test case */
-         goto decode_failure;
+         addr = disAMode ( &alen, sorb, delta+2, dis_buf );
+         delta += 3+alen;
+         lane = insn[3+alen-1];
+         assign(t4, loadLE(Ity_I16, mkexpr(addr)));
+         DIP("pinsrw $%d,%s,%s\n", (Int)lane, 
+                                   dis_buf,
+                                   nameMMXReg(gregOfRM(modrm)));
       }
 
       switch (lane & 3) {