commit 774b88bb034bf118b1a6c37d9e930e22caa297f2
author sewardj <sewardj@8f6e269a-dfd6-0310-a8e1-e2731360e62c> Mon Oct 11 18:03:13 2010 +0000
committer sewardj <sewardj@8f6e269a-dfd6-0310-a8e1-e2731360e62c> Mon Oct 11 18:03:13 2010 +0000
tree 0dd8a01013bf0787674f1c2a2a0e2527436c2e7d
parent b0d80eab1a0c5bf1c119879d9de341aa47da9572

Fix bogus register constraints for ARM mode LDREX and STREX.
Derived from a patch by Rodrigo Belem <rodrigo.belem@openbossa.org>
Partially fixes #253636.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2063 8f6e269a-dfd6-0310-a8e1-e2731360e62c

priv/guest_arm_toIR.c

diff --git a/priv/guest_arm_toIR.c b/priv/guest_arm_toIR.c
index 64a059d..4e1d740 100644
--- a/priv/guest_arm_toIR.c
+++ b/priv/guest_arm_toIR.c
@@ -13287,7 +13287,7 @@
    if (0x01900F9F == (insn & 0x0FF00FFF)) {
       UInt rT = INSN(15,12);
       UInt rN = INSN(19,16);
-      if (rT == 15 || rN == 15 || rT == 14 /* || (rT & 1)*/) {
+      if (rT == 15 || rN == 15) {
          /* undecodable; fall through */
       } else {
          IRTemp res;
@@ -13313,8 +13313,7 @@
       UInt rN = INSN(19,16);
       UInt rD = INSN(15,12);
       if (rT == 15 || rN == 15 || rD == 15
-          || rT == 14 /* || (rT & 1)*/
-          || rD == rT || rN == rT) {
+          || rD == rT || rD == rN) {
          /* undecodable; fall through */
       } else {
          IRTemp resSC1, resSC32;