mips32/mips64: additional VEX support for FCSR register.
Some mips fpu instructions are changing the value of the
fcsr register so we need to update the value of the fcsr
register in the guest state.
git-svn-id: svn://svn.valgrind.org/vex/trunk@2766 8f6e269a-dfd6-0310-a8e1-e2731360e62c
diff --git a/priv/host_mips_isel.c b/priv/host_mips_isel.c
index d59b4ab..06c1eb5 100644
--- a/priv/host_mips_isel.c
+++ b/priv/host_mips_isel.c
@@ -554,7 +554,7 @@
if (LIKELY(!is_IRExpr_VECRET_or_BBPTR(arg)))
aTy = typeOfIRExpr(env->type_env, arg);
- if (aTy == Ity_I32 || mode64) {
+ if (aTy == Ity_I32 || (mode64 && arg->tag != Iex_BBPTR)) {
tmpregs[argreg] = iselWordExpr_R(env, arg);
argreg++;
} else if (aTy == Ity_I64) { /* Ity_I64 */
@@ -569,7 +569,6 @@
tmpregs[argreg] = raHi;
argreg++;
} else if (arg->tag == Iex_BBPTR) {
- vassert(0); // ATC
tmpregs[argreg] = GuestStatePointer(mode64);
argreg++;
}