Move the handling of PSHUFW from the SSE code to the MMX code so that
it will work on older Athlons which only have MMXEXT support.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@2319 a5019735-40e9-0310-863c-91ae7b9d1cf9
diff --git a/cachegrind/cg_main.c b/cachegrind/cg_main.c
index 2f83e76..a0641dd 100644
--- a/cachegrind/cg_main.c
+++ b/cachegrind/cg_main.c
@@ -604,6 +604,13 @@
is_FPU_R = True;
break;
+ case MMX2a1_MemRd:
+ sk_assert(u_in->size == 8);
+ sk_assert(!is_LOAD && !is_STORE && !is_FPU_R && !is_FPU_W);
+ t_read = u_in->val3;
+ is_FPU_R = True;
+ break;
+
case SSE2a_MemRd:
case SSE2a1_MemRd:
sk_assert(u_in->size == 4 || u_in->size == 8 || u_in->size == 16 || u_in->size == 512);
@@ -857,6 +864,18 @@
: MIN_LINE_SIZE);
VG_(copy_UInstr)(cb, u_in);
break;
+ break;
+
+ case MMX2a1_MemRd:
+ sk_assert(u_in->size == 8);
+ t_read = u_in->val3;
+ t_read_addr = newTemp(cb);
+ uInstr2(cb, MOV, 4, TempReg, u_in->val3, TempReg, t_read_addr);
+ data_size = ( u_in->size <= MIN_LINE_SIZE
+ ? u_in->size
+ : MIN_LINE_SIZE);
+ VG_(copy_UInstr)(cb, u_in);
+ break;
case SSE2a_MemRd:
case SSE2a1_MemRd: