Merged FORMATCHECK branch (r8368) to trunk.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@8369 a5019735-40e9-0310-863c-91ae7b9d1cf9
diff --git a/callgrind/sim.c b/callgrind/sim.c
index 7c14fd6..3d9ae6c 100644
--- a/callgrind/sim.c
+++ b/callgrind/sim.c
@@ -691,7 +691,7 @@
c->use[idx].count ++;
c->use[idx].mask |= use_mask;
- CLG_DEBUG(6," Hit [idx %d] (line %p from %p): %x => %08x, count %d\n",
+ CLG_DEBUG(6," Hit [idx %d] (line %#lx from %#lx): %x => %08x, count %d\n",
idx, c->loaded[idx].memline, c->loaded[idx].iaddr,
use_mask, c->use[idx].mask, c->use[idx].count);
}
@@ -790,7 +790,7 @@
UWord *set, tmp_tag; \
UInt use_mask; \
\
- CLG_DEBUG(6,"%s.Acc(Addr %p, size %d): Sets [%d/%d]\n", \
+ CLG_DEBUG(6,"%s.Acc(Addr %#lx, size %d): Sets [%d/%d]\n", \
L.name, a, size, set1, set2); \
\
/* First case: word entirely within line. */ \
@@ -808,7 +808,7 @@
idx = (set1 << L.assoc_bits) | (set[0] & ~L.tag_mask); \
L.use[idx].count ++; \
L.use[idx].mask |= use_mask; \
- CLG_DEBUG(6," Hit0 [idx %d] (line %p from %p): %x => %08x, count %d\n",\
+ CLG_DEBUG(6," Hit0 [idx %d] (line %#lx from %#lx): %x => %08x, count %d\n",\
idx, L.loaded[idx].memline, L.loaded[idx].iaddr, \
use_mask, L.use[idx].mask, L.use[idx].count); \
return L1_Hit; \
@@ -825,7 +825,7 @@
idx = (set1 << L.assoc_bits) | (tmp_tag & ~L.tag_mask); \
L.use[idx].count ++; \
L.use[idx].mask |= use_mask; \
- CLG_DEBUG(6," Hit%d [idx %d] (line %p from %p): %x => %08x, count %d\n",\
+ CLG_DEBUG(6," Hit%d [idx %d] (line %#lx from %#lx): %x => %08x, count %d\n",\
i, idx, L.loaded[idx].memline, L.loaded[idx].iaddr, \
use_mask, L.use[idx].mask, L.use[idx].count); \
return L1_Hit; \
@@ -852,7 +852,7 @@
idx = (set1 << L.assoc_bits) | (set[0] & ~L.tag_mask); \
L.use[idx].count ++; \
L.use[idx].mask |= use_mask; \
- CLG_DEBUG(6," Hit0 [idx %d] (line %p from %p): %x => %08x, count %d\n",\
+ CLG_DEBUG(6," Hit0 [idx %d] (line %#lx from %#lx): %x => %08x, count %d\n",\
idx, L.loaded[idx].memline, L.loaded[idx].iaddr, \
use_mask, L.use[idx].mask, L.use[idx].count); \
goto block2; \
@@ -867,7 +867,7 @@
idx = (set1 << L.assoc_bits) | (tmp_tag & ~L.tag_mask); \
L.use[idx].count ++; \
L.use[idx].mask |= use_mask; \
- CLG_DEBUG(6," Hit%d [idx %d] (line %p from %p): %x => %08x, count %d\n",\
+ CLG_DEBUG(6," Hit%d [idx %d] (line %#lx from %#lx): %x => %08x, count %d\n",\
i, idx, L.loaded[idx].memline, L.loaded[idx].iaddr, \
use_mask, L.use[idx].mask, L.use[idx].count); \
goto block2; \
@@ -889,7 +889,7 @@
idx = (set2 << L.assoc_bits) | (set[0] & ~L.tag_mask); \
L.use[idx].count ++; \
L.use[idx].mask |= use_mask; \
- CLG_DEBUG(6," Hit0 [idx %d] (line %p from %p): %x => %08x, count %d\n",\
+ CLG_DEBUG(6," Hit0 [idx %d] (line %#lx from %#lx): %x => %08x, count %d\n",\
idx, L.loaded[idx].memline, L.loaded[idx].iaddr, \
use_mask, L.use[idx].mask, L.use[idx].count); \
return miss1; \
@@ -904,7 +904,7 @@
idx = (set2 << L.assoc_bits) | (tmp_tag & ~L.tag_mask); \
L.use[idx].count ++; \
L.use[idx].mask |= use_mask; \
- CLG_DEBUG(6," Hit%d [idx %d] (line %p from %p): %x => %08x, count %d\n",\
+ CLG_DEBUG(6," Hit%d [idx %d] (line %#lx from %#lx): %x => %08x, count %d\n",\
i, idx, L.loaded[idx].memline, L.loaded[idx].iaddr, \
use_mask, L.use[idx].mask, L.use[idx].count); \
return miss1; \
@@ -921,7 +921,7 @@
return (miss1==MemAccess || miss2==MemAccess) ? MemAccess:L2_Hit; \
\
} else { \
- VG_(printf)("addr: %p size: %u sets: %d %d", a, size, set1, set2); \
+ VG_(printf)("addr: %#lx size: %u sets: %d %d", a, size, set1, set2); \
VG_(tool_panic)("item straddles more than two cache sets"); \
} \
return 0; \
@@ -952,10 +952,10 @@
line_use* use = &(L2.use[idx]);
int i = ((32 - countBits(use->mask)) * L2.line_size)>>5;
- CLG_DEBUG(2, " L2.miss [%d]: at %p accessing memline %p\n",
+ CLG_DEBUG(2, " L2.miss [%d]: at %#lx accessing memline %#lx\n",
idx, bb_base + current_ii->instr_offset, memline);
if (use->count>0) {
- CLG_DEBUG(2, " old: used %d, loss bits %d (%08x) [line %p from %p]\n",
+ CLG_DEBUG(2, " old: used %d, loss bits %d (%08x) [line %#lx from %#lx]\n",
use->count, i, use->mask, loaded->memline, loaded->iaddr);
CLG_DEBUG(2, " collect: %d, use_base %p\n",
CLG_(current_state).collect, loaded->use_base);
@@ -986,13 +986,13 @@
int i, j, idx;
UWord tmp_tag;
- CLG_DEBUG(6,"L2.Acc(Memline %p): Set %d\n", memline, setNo);
+ CLG_DEBUG(6,"L2.Acc(Memline %#lx): Set %d\n", memline, setNo);
if (tag == (set[0] & L2.tag_mask)) {
idx = (setNo << L2.assoc_bits) | (set[0] & ~L2.tag_mask);
l1_loaded->dep_use = &(L2.use[idx]);
- CLG_DEBUG(6," Hit0 [idx %d] (line %p from %p): => %08x, count %d\n",
+ CLG_DEBUG(6," Hit0 [idx %d] (line %#lx from %#lx): => %08x, count %d\n",
idx, L2.loaded[idx].memline, L2.loaded[idx].iaddr,
L2.use[idx].mask, L2.use[idx].count);
return L2_Hit;
@@ -1007,7 +1007,7 @@
idx = (setNo << L2.assoc_bits) | (tmp_tag & ~L2.tag_mask);
l1_loaded->dep_use = &(L2.use[idx]);
- CLG_DEBUG(6," Hit%d [idx %d] (line %p from %p): => %08x, count %d\n",
+ CLG_DEBUG(6," Hit%d [idx %d] (line %#lx from %#lx): => %08x, count %d\n",
i, idx, L2.loaded[idx].memline, L2.loaded[idx].iaddr,
L2.use[idx].mask, L2.use[idx].count);
return L2_Hit;
@@ -1040,10 +1040,10 @@
line_use* use = &(cache->use[idx]); \
int c = ((32 - countBits(use->mask)) * cache->line_size)>>5; \
\
- CLG_DEBUG(2, " %s.miss [%d]: at %p accessing memline %p (mask %08x)\n", \
+ CLG_DEBUG(2, " %s.miss [%d]: at %#lx accessing memline %#lx (mask %08x)\n", \
cache->name, idx, bb_base + current_ii->instr_offset, memline, mask); \
if (use->count>0) { \
- CLG_DEBUG(2, " old: used %d, loss bits %d (%08x) [line %p from %p]\n",\
+ CLG_DEBUG(2, " old: used %d, loss bits %d (%08x) [line %#lx from %#lx]\n",\
use->count, c, use->mask, loaded->memline, loaded->iaddr); \
CLG_DEBUG(2, " collect: %d, use_base %p\n", \
CLG_(current_state).collect, loaded->use_base); \
@@ -1149,7 +1149,7 @@
current_ii = ii;
IrRes = (*simulator.I1_Read)(bb_base + ii->instr_offset, ii->instr_size);
- CLG_DEBUG(6, "log_1I0D: Ir=%p/%u => Ir %d\n",
+ CLG_DEBUG(6, "log_1I0D: Ir=%#lx/%u => Ir %d\n",
bb_base + ii->instr_offset, ii->instr_size, IrRes);
if (CLG_(current_state).collect) {
@@ -1177,7 +1177,7 @@
IrRes = (*simulator.I1_Read)(bb_base + ii->instr_offset, ii->instr_size);
DrRes = (*simulator.D1_Read)(data, ii->data_size);
- CLG_DEBUG(6, "log_1I1Dr: Ir=%p/%u, Dr=%p/%u => Ir %d, Dr %d\n",
+ CLG_DEBUG(6, "log_1I1Dr: Ir=%#lx/%u, Dr=%#lx/%u => Ir %d, Dr %d\n",
bb_base + ii->instr_offset, ii->instr_size,
data, ii->data_size, IrRes, DrRes);
@@ -1209,7 +1209,7 @@
current_ii = ii;
DrRes = (*simulator.D1_Read)(data, ii->data_size);
- CLG_DEBUG(6, "log_0I1Dr: Dr=%p/%u => Dr %d\n",
+ CLG_DEBUG(6, "log_0I1Dr: Dr=%#lx/%u => Dr %d\n",
data, ii->data_size, DrRes);
if (CLG_(current_state).collect) {
@@ -1239,7 +1239,7 @@
IrRes = (*simulator.I1_Read)(bb_base + ii->instr_offset, ii->instr_size);
DwRes = (*simulator.D1_Write)(data, ii->data_size);
- CLG_DEBUG(6, "log_1I1Dw: Ir=%p/%u, Dw=%p/%u => Ir %d, Dw %d\n",
+ CLG_DEBUG(6, "log_1I1Dw: Ir=%#lx/%u, Dw=%#lx/%u => Ir %d, Dw %d\n",
bb_base + ii->instr_offset, ii->instr_size,
data, ii->data_size, IrRes, DwRes);
@@ -1270,7 +1270,7 @@
current_ii = ii;
DwRes = (*simulator.D1_Write)(data, ii->data_size);
- CLG_DEBUG(6, "log_0I1Dw: Dw=%p/%u => Dw %d\n",
+ CLG_DEBUG(6, "log_0I1Dw: Dw=%#lx/%u => Dw %d\n",
data, ii->data_size, DwRes);
if (CLG_(current_state).collect) {
@@ -1301,7 +1301,7 @@
DwRes = (*simulator.D1_Write)(data2, ii->data_size);
CLG_DEBUG(6,
- "log_1I2D: Ir=%p/%u, Dr=%p/%u, Dw=%p/%u => Ir %d, Dr %d, Dw %d\n",
+ "log_1I2D: Ir=%#lx/%u, Dr=%#lx/%u, Dw=%#lx/%u => Ir %d, Dr %d, Dw %d\n",
bb_base + ii->instr_offset, ii->instr_size,
data1, ii->data_size, data2, ii->data_size, IrRes, DrRes, DwRes);
@@ -1338,7 +1338,7 @@
DwRes = (*simulator.D1_Write)(data2, ii->data_size);
CLG_DEBUG(6,
- "log_0D2D: Dr=%p/%u, Dw=%p/%u => Dr %d, Dw %d\n",
+ "log_0D2D: Dr=%#lx/%u, Dw=%#lx/%u => Dr %d, Dw %d\n",
data1, ii->data_size, data2, ii->data_size, DrRes, DwRes);
if (CLG_(current_state).collect) {