commit abf8bf8404afd13a48f1b45f690dda239c2aa0de
author sewardj <sewardj@a5019735-40e9-0310-863c-91ae7b9d1cf9> Sun Jun 15 22:28:05 2003 +0000
committer sewardj <sewardj@a5019735-40e9-0310-863c-91ae7b9d1cf9> Sun Jun 15 22:28:05 2003 +0000
tree bea374274d25f09b9e6f733420a9a9522a136657
parent 4fbe6e9ff89567e4c8cc7fdf579ad5b8c25ce1d0

- Continue to clear up SSE insn emitters following recent cleanups re
  G vs E register fields in encoding
- Add SSE3e_RegWr and use it to implement a case in MOVD.


git-svn-id: svn://svn.valgrind.org/valgrind/trunk@1699 a5019735-40e9-0310-863c-91ae7b9d1cf9

coregrind/vg_translate.c

diff --git a/coregrind/vg_translate.c b/coregrind/vg_translate.c
index 5a5dfd4..d0b0458 100644
--- a/coregrind/vg_translate.c
+++ b/coregrind/vg_translate.c
@@ -564,6 +564,7 @@
    case SSE3a_MemWr:  return LIT0 && SZsse && CC0  && Ls1 && Ls2 && TR3 && XOTHER;
    case SSE3a_MemRd:  return LIT0 && SZsse && CCf  && Ls1 && Ls2 && TR3 && XOTHER;
    case SSE3e_RegRd:  return LIT0 && SZ4   && CC0  && Ls1 && Ls2 && TR3 && XOTHER;
+   case SSE3e_RegWr:  return LIT0 && SZ4   && CC0  && Ls1 && Ls2 && TR3 && XOTHER;
    case SSE3g_RegWr:  return LIT0 && SZ4   && CC0  && Ls1 && Ls2 && TR3 && XOTHER;
    case SSE3g1_RegWr: return LIT8 && SZ4   && CC0  && Ls1 && Ls2 && TR3 && XOTHER;
    case SSE3e1_RegRd: return LIT8 && SZ2   && CC0  && Ls1 && Ls2 && TR3 && XOTHER;
@@ -887,6 +888,7 @@
       case SSE2a_MemWr: return "SSE2a_MWr";
       case SSE2a_MemRd: return "SSE2a_MRd";
       case SSE3e_RegRd: return "SSE3e_RRd";
+      case SSE3e_RegWr: return "SSE3e_RWr";
       case SSE3g_RegWr: return "SSE3g_RWr";
       case SSE3g1_RegWr: return "SSE3g1_RWr";
       case SSE3e1_RegRd: return "SSE3e1_RRd";
@@ -1061,6 +1063,7 @@
          VG_(pp_UOperand)(u, 3, 4, True);
          break;
 
+      case SSE3e_RegWr:
       case SSE3e_RegRd:
       case SSE3g_RegWr:
          VG_(printf)("0x%x:0x%x:0x%x:0x%x",
@@ -1257,6 +1260,7 @@
       case SSE3e1_RegRd:
       case SSE2a_MemRd: RD(3); break;
 
+      case SSE3e_RegWr:
       case SSE3g1_RegWr:
       case SSE3g_RegWr: WR(3); break;
 
@@ -1419,7 +1423,7 @@
       case MMX2_ERegRd: case MMX2_ERegWr:
       case SSE2a_MemWr: case SSE2a_MemRd:
       case SSE3a_MemWr: case SSE3a_MemRd:
-      case SSE3e_RegRd: case SSE3g_RegWr: 
+      case SSE3e_RegRd: case SSE3g_RegWr: case SSE3e_RegWr:
       case SSE3g1_RegWr: case SSE3e1_RegRd:
       case SSE4: case SSE3: case SSE5: case SSE3ag_MemRd_RegWr:
       case WIDEN: