Fill in enough cases to run switchback/test_bzip2.c on amd64.
git-svn-id: svn://svn.valgrind.org/vex/trunk@904 8f6e269a-dfd6-0310-a8e1-e2731360e62c
diff --git a/priv/guest-amd64/toIR.c b/priv/guest-amd64/toIR.c
index 73a6f50..e421454 100644
--- a/priv/guest-amd64/toIR.c
+++ b/priv/guest-amd64/toIR.c
@@ -11307,19 +11307,21 @@
//.. DIP("mov%c %s, %s0x%x\n", nameISize(sz), nameIReg(sz,R_EAX),
//.. sorbTxt(sorb), d32);
//.. break;
-//..
+
+/* XXXX be careful here with moves to AH/BH/CH/DH */
//.. case 0xB0: /* MOV imm,AL */
//.. case 0xB1: /* MOV imm,CL */
-//.. case 0xB2: /* MOV imm,DL */
+ case 0xB2: /* MOV imm,DL */
//.. case 0xB3: /* MOV imm,BL */
//.. case 0xB4: /* MOV imm,AH */
//.. case 0xB5: /* MOV imm,CH */
//.. case 0xB6: /* MOV imm,DH */
//.. case 0xB7: /* MOV imm,BH */
-//.. d32 = getUChar(delta); delta += 1;
-//.. putIReg(1, opc-0xB0, mkU8(d32));
-//.. DIP("movb $0x%x,%s\n", d32, nameIReg(1,opc-0xB0));
-//.. break;
+ d64 = getUChar(delta);
+ delta += 1;
+ putIRegB(pfx, 1, opc-0xB0, mkU8(d64));
+ DIP("movb $%lld,%s\n", d64, nameIRegB(pfx,1,opc-0xB0));
+ break;
case 0xB8: /* MOV imm,eAX */
case 0xB9: /* MOV imm,eCX */
@@ -11536,9 +11538,10 @@
delta = dis_op2_E_G ( pfx, False, Iop_Xor8, True, sz, delta, "xor" );
break;
-//.. case 0x3A: /* CMP Eb,Gb */
-//.. delta = dis_op2_E_G ( sorb, False, Iop_Sub8, False, 1, delta, "cmp" );
-//.. break;
+ case 0x3A: /* CMP Eb,Gb */
+ if (haveF2orF3(pfx)) goto decode_failure;
+ delta = dis_op2_E_G ( pfx, False, Iop_Sub8, False, 1, delta, "cmp" );
+ break;
case 0x3B: /* CMP Ev,Gv */
if (haveF2orF3(pfx)) goto decode_failure;
delta = dis_op2_E_G ( pfx, False, Iop_Sub8, False, sz, delta, "cmp" );
@@ -11603,9 +11606,10 @@
delta = dis_op2_G_E ( pfx, False, Iop_Sub8, True, sz, delta, "sub" );
break;
-//.. case 0x30: /* XOR Gb,Eb */
-//.. delta = dis_op2_G_E ( sorb, False, Iop_Xor8, True, 1, delta, "xor" );
-//.. break;
+ case 0x30: /* XOR Gb,Eb */
+ if (haveF2orF3(pfx)) goto decode_failure;
+ delta = dis_op2_G_E ( pfx, False, Iop_Xor8, True, 1, delta, "xor" );
+ break;
case 0x31: /* XOR Gv,Ev */
if (haveF2orF3(pfx)) goto decode_failure;
delta = dis_op2_G_E ( pfx, False, Iop_Xor8, True, sz, delta, "xor" );
diff --git a/priv/host-amd64/isel.c b/priv/host-amd64/isel.c
index f2c0b48..4e235af 100644
--- a/priv/host-amd64/isel.c
+++ b/priv/host-amd64/isel.c
@@ -827,6 +827,8 @@
switch (e->Iex.Binop.op) {
case Iop_Shr64: case Iop_Shl64: case Iop_Sar64:
break;
+ case Iop_Shl32:
+ break;
//.. case Iop_Shr8:
//.. addInstr(env, X86Instr_Alu32R(
//.. Xalu_AND, X86RMI_Imm(0xFF), dst));
@@ -835,6 +837,10 @@
//.. addInstr(env, X86Instr_Alu32R(
//.. Xalu_AND, X86RMI_Imm(0xFFFF), dst));
//.. break;
+ case Iop_Shr32:
+ addInstr(env, AMD64Instr_Alu64R(
+ Aalu_AND, AMD64RMI_Imm(0xFFFFFFFF), dst));
+ break;
//.. case Iop_Sar8:
//.. addInstr(env, X86Instr_Sh32(Xsh_SHL, 24, X86RM_Reg(dst)));
//.. addInstr(env, X86Instr_Sh32(Xsh_SAR, 24, X86RM_Reg(dst)));
diff --git a/priv/ir/iropt.c b/priv/ir/iropt.c
index 4c22559..6b64e92 100644
--- a/priv/ir/iropt.c
+++ b/priv/ir/iropt.c
@@ -1022,6 +1022,7 @@
(e->Iex.Binop.arg1->Iex.Const.con->Ico.U32
* e->Iex.Binop.arg2->Iex.Const.con->Ico.U32)));
break;
+
case Iop_Shl32:
vassert(e->Iex.Binop.arg2->Iex.Const.con->tag == Ico_U8);
shift = (Int)(e->Iex.Binop.arg2->Iex.Const.con->Ico.U8);
@@ -1030,6 +1031,15 @@
(e->Iex.Binop.arg1->Iex.Const.con->Ico.U32
<< shift)));
break;
+ case Iop_Shl64:
+ vassert(e->Iex.Binop.arg2->Iex.Const.con->tag == Ico_U8);
+ shift = (Int)(e->Iex.Binop.arg2->Iex.Const.con->Ico.U8);
+ if (shift >= 0 && shift <= 63)
+ e2 = IRExpr_Const(IRConst_U64(
+ (e->Iex.Binop.arg1->Iex.Const.con->Ico.U64
+ << shift)));
+ break;
+
case Iop_Sar32: {
/* paranoid ... */
/*signed*/ Int s32;