Merge cachegrind/ changes from branches/MESSAGING_TIDYUP r10464.
See trunk r10465 commit message for details.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@10472 a5019735-40e9-0310-863c-91ae7b9d1cf9
diff --git a/cachegrind/cg-x86-amd64.c b/cachegrind/cg-x86-amd64.c
index 821a8c7..b94ea14 100644
--- a/cachegrind/cg-x86-amd64.c
+++ b/cachegrind/cg-x86-amd64.c
@@ -44,10 +44,10 @@
static void micro_ops_warn(Int actual_size, Int used_size, Int line_size)
{
- VG_DMSG("warning: Pentium 4 with %d KB micro-op instruction trace cache",
- actual_size);
- VG_DMSG(" Simulating a %d KB I-cache with %d B lines",
- used_size, line_size);
+ VG_(dmsg)("warning: Pentium 4 with %d KB micro-op instruction trace cache\n",
+ actual_size);
+ VG_(dmsg)(" Simulating a %d KB I-cache with %d B lines\n",
+ used_size, line_size);
}
/* Intel method is truly wretched. We have to do an insane indexing into an
@@ -67,7 +67,7 @@
Bool L2_found = False;
if (level < 2) {
- VG_DMSG("warning: CPUID level < 2 for Intel processor (%d)", level);
+ VG_(dmsg)("warning: CPUID level < 2 for Intel processor (%d)\n", level);
return -1;
}
@@ -83,8 +83,8 @@
info[0] = 0x0; /* reset AL */
if (0 != trials) {
- VG_DMSG("warning: non-zero CPUID trials for Intel processor (%d)",
- trials);
+ VG_(dmsg)("warning: non-zero CPUID trials for Intel processor (%d)\n",
+ trials);
return -1;
}
@@ -121,7 +121,7 @@
case 0x22: case 0x23: case 0x25: case 0x29:
case 0x46: case 0x47: case 0x4a: case 0x4b: case 0x4c: case 0x4d:
- VG_DMSG("warning: L3 cache detected but ignored");
+ VG_(dmsg)("warning: L3 cache detected but ignored\n");
break;
/* These are sectored, whatever that means */
@@ -144,7 +144,7 @@
case 0x49:
if ((family == 15) && (model == 6))
/* On Xeon MP (family F, model 6), this is for L3 */
- VG_DMSG("warning: L3 cache detected but ignored");
+ VG_(dmsg)("warning: L3 cache detected but ignored\n");
else
*L2c = (cache_t) { 4096, 16, 64 }; L2_found = True;
break;
@@ -198,14 +198,14 @@
break;
default:
- VG_DMSG("warning: Unknown Intel cache config value (0x%x), ignoring",
- info[i]);
+ VG_(dmsg)("warning: Unknown Intel cache config value (0x%x), ignoring\n",
+ info[i]);
break;
}
}
if (!L2_found)
- VG_DMSG("warning: L2 cache not installed, ignore L2 results.");
+ VG_(dmsg)("warning: L2 cache not installed, ignore L2 results.\n");
return 0;
}
@@ -244,8 +244,8 @@
VG_(cpuid)(0x80000000, &ext_level, &dummy, &dummy, &dummy);
if (0 == (ext_level & 0x80000000) || ext_level < 0x80000006) {
- VG_DMSG("warning: ext_level < 0x80000006 for AMD processor (0x%x)",
- ext_level);
+ VG_(dmsg)("warning: ext_level < 0x80000006 for AMD processor (0x%x)\n",
+ ext_level);
return -1;
}
@@ -256,7 +256,7 @@
/* Check for Duron bug */
if (model == 0x630) {
- VG_DMSG("warning: Buggy Duron stepping A0. Assuming L2 size=65536 bytes");
+ VG_(dmsg)("warning: Buggy Duron stepping A0. Assuming L2 size=65536 bytes\n");
L2i = (64 << 16) | (L2i & 0xffff);
}
@@ -282,7 +282,7 @@
Char vendor_id[13];
if (!VG_(has_cpuid)()) {
- VG_DMSG("CPUID instruction not supported");
+ VG_(dmsg)("CPUID instruction not supported\n");
return -1;
}
@@ -291,7 +291,7 @@
vendor_id[12] = '\0';
if (0 == level) {
- VG_DMSG("CPUID level is 0, early Pentium?");
+ VG_(dmsg)("CPUID level is 0, early Pentium?\n");
return -1;
}
@@ -316,7 +316,7 @@
ret = 0;
} else {
- VG_DMSG("CPU vendor ID not recognised (%s)", vendor_id);
+ VG_(dmsg)("CPU vendor ID not recognised (%s)\n", vendor_id);
return -1;
}
@@ -344,8 +344,8 @@
// Warn if CPUID failed and config not completely specified from cmd line.
if (res != 0 && !all_caches_clo_defined) {
- VG_DMSG("Warning: Couldn't auto-detect cache config, using one "
- "or more defaults ");
+ VG_(dmsg)("Warning: Couldn't auto-detect cache config, using one "
+ "or more defaults \n");
}
}