Update cache simulator for 64 bit addresses. This probably won't have
caused many inaccuracies so far because it only matters if addresses
above the 4GB line are used. Thanks to Josef W for the patch.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@4898 a5019735-40e9-0310-863c-91ae7b9d1cf9
diff --git a/cachegrind/cg_sim.c b/cachegrind/cg_sim.c
index 36b449b..a5c65df 100644
--- a/cachegrind/cg_sim.c
+++ b/cachegrind/cg_sim.c
@@ -48,7 +48,7 @@
int line_size_bits;
int tag_shift;
char desc_line[128];
- int* tags;
+ UWord* tags;
} cache_t2;
/* By this point, the size/assoc/line_size has been checked. */
@@ -74,7 +74,7 @@
c->size, c->line_size, c->assoc);
}
- c->tags = VG_(malloc)(sizeof(UInt) * c->sets * c->assoc);
+ c->tags = VG_(malloc)(sizeof(UWord) * c->sets * c->assoc);
for (i = 0; i < c->sets * c->assoc; i++)
c->tags[i] = 0;
@@ -88,7 +88,7 @@
/* Note initialisation and update of 'i'. */
for (i = 0, set = 0; set < c->sets; set++) {
for (way = 0; way < c->assoc; way++, i++) {
- VG_(printf)("%8x ", c->tags[i]);
+ VG_(printf)("%16lx ", c->tags[i]);
}
VG_(printf)("\n");
}
@@ -111,12 +111,12 @@
static /* __inline__ */ \
void cachesim_##L##_doref(Addr a, UChar size, ULong* m1, ULong *m2) \
{ \
- register UInt set1 = ( a >> L.line_size_bits) & (L.sets_min_1); \
- register UInt set2 = ((a+size-1) >> L.line_size_bits) & (L.sets_min_1); \
- register UInt tag = a >> L.tag_shift; \
+ register UInt set1 = ( a >> L.line_size_bits) & (L.sets_min_1); \
+ register UInt set2 = ((a+size-1) >> L.line_size_bits) & (L.sets_min_1); \
+ register UWord tag = a >> L.tag_shift; \
int i, j; \
Bool is_miss = False; \
- int* set; \
+ UWord* set; \
\
/* First case: word entirely within line. */ \
if (set1 == set2) { \