commit c76d0e5cf15d9a352c39a72867ae1c41875c6bb0
author sewardj <sewardj@a5019735-40e9-0310-863c-91ae7b9d1cf9> Sat May 03 21:22:55 2014 +0000
committer sewardj <sewardj@a5019735-40e9-0310-863c-91ae7b9d1cf9> Sat May 03 21:22:55 2014 +0000
tree b07d58a7f5ab3c223b891a9394fc4b8020b65bf3
parent f57743408d27fedf60a7b48d25339d51b1f8a055

ARM64: add support for cache management instructions (Valgrind side):
  dc cvau, regX
  ic ivau, regX
  mrs regX, ctr_el0
Fixes #333228 and #333230.



git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13931 a5019735-40e9-0310-863c-91ae7b9d1cf9

memcheck/mc_machine.c

diff --git a/memcheck/mc_machine.c b/memcheck/mc_machine.c
index e385310..e8a15f4 100644
--- a/memcheck/mc_machine.c
+++ b/memcheck/mc_machine.c
@@ -1055,6 +1055,9 @@
    if (o == GOF(FPCR) && sz == 4) return -1; // untracked
    if (o == GOF(FPSR) && sz == 4) return -1; // untracked
 
+   if (o == GOF(TISTART) && sz == 8) return -1; // untracked
+   if (o == GOF(TILEN)   && sz == 8) return -1; // untracked
+
    VG_(printf)("MC_(get_otrack_shadow_offset)(arm64)(off=%d,sz=%d)\n",
                offset,szB);
    tl_assert(0);