diff --git a/pub/libvex_emwarn.h b/pub/libvex_emwarn.h
index 1fd7e37..9b1c6ac 100644
--- a/pub/libvex_emwarn.h
+++ b/pub/libvex_emwarn.h
@@ -57,16 +57,15 @@
    enum {
       /* no warning indicated */
       EmWarn_NONE=0,
+
       /* unmasking x87 FP exceptions is not supported */
       EmWarn_X86_x87exns,
-      /* use of unsupported x87 FP rounding mode */
-      EmWarn_X86_x87rounding,
+
       /* change of x87 FP precision away from 64-bit (mantissa) */
       EmWarn_X86_x87precision,
+
       /* unmasking SSE FP exceptions is not supported */
       EmWarn_X86_sseExns,
-      /* use of unsupported SSE FP rounding mode */
-      EmWarn_X86_sseRounding,
       
       EmWarn_NUMBER
    }
diff --git a/pub/libvex_guest_x86.h b/pub/libvex_guest_x86.h
index ac7dfa2..e3ddfed 100644
--- a/pub/libvex_guest_x86.h
+++ b/pub/libvex_guest_x86.h
@@ -91,9 +91,11 @@
    * fst from st(0) to st(i) does not take an overflow fault even if the
      destination is already full.
 
-   FPRTZ[0] is the FPU's notional rounding mode -- 0 "to nearest" (the
-   default), 1 "to zero".  FPRTZ[31:1] is unused.  Round to
-   +infinity/-infinity is not supported.
+   FPROUND[1:0] is the FPU's notional rounding mode, encoded as per
+   the IRRoundingMode type (see libvex_ir.h).  This just happens to be
+   the Intel encoding.  Note carefully, the rounding mode is only
+   observed on float-to-int conversions, and not for float-to-float
+   operations.
 
    FC3210 contains the C3, C2, C1 and C0 bits in the same place they
    are in the FPU's status word.  (bits 14, 10, 9, 8 respectively).
@@ -126,7 +128,7 @@
       UInt  guest_FTOP;
       ULong guest_FPREG[8];
       UChar guest_FPTAG[8];
-      UInt  guest_FPRTZ;
+      UInt  guest_FPROUND;
       UInt  guest_FC3210;
       /* Segment registers. */
       UShort guest_CS;