Track vex r1930 (Change the IR representation of load linked and store
conditional.) Completes the fix of #215771.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@10957 a5019735-40e9-0310-863c-91ae7b9d1cf9
diff --git a/cachegrind/cg_main.c b/cachegrind/cg_main.c
index 50d388c..391d47a 100644
--- a/cachegrind/cg_main.c
+++ b/cachegrind/cg_main.c
@@ -1053,6 +1053,22 @@
break;
}
+ case Ist_LLSC: {
+ IRType dataTy;
+ if (st->Ist.LLSC.storedata == NULL) {
+ /* LL */
+ dataTy = typeOfIRTemp(tyenv, st->Ist.LLSC.result);
+ addEvent_Dr( &cgs, curr_inode,
+ sizeofIRType(dataTy), st->Ist.LLSC.addr );
+ } else {
+ /* SC */
+ dataTy = typeOfIRExpr(tyenv, st->Ist.LLSC.storedata);
+ addEvent_Dw( &cgs, curr_inode,
+ sizeofIRType(dataTy), st->Ist.LLSC.addr );
+ }
+ break;
+ }
+
case Ist_Exit: {
/* Stuff to widen the guard expression to a host word, so
we can pass it to the branch predictor simulation