Track vex r1930 (Change the IR representation of load linked and store
conditional.) Completes the fix of #215771.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@10957 a5019735-40e9-0310-863c-91ae7b9d1cf9
diff --git a/helgrind/hg_main.c b/helgrind/hg_main.c
index 31cec56..d2f34b6 100644
--- a/helgrind/hg_main.c
+++ b/helgrind/hg_main.c
@@ -4008,19 +4008,41 @@
break;
}
- case Ist_Store:
- /* It seems we pretend that store-conditionals don't
- exist, viz, just ignore them ... */
- if (st->Ist.Store.resSC == IRTemp_INVALID) {
+ case Ist_LLSC: {
+ /* We pretend store-conditionals don't exist, viz, ignore
+ them. Whereas load-linked's are treated the same as
+ normal loads. */
+ IRType dataTy;
+ if (st->Ist.LLSC.storedata == NULL) {
+ /* LL */
+ dataTy = typeOfIRTemp(bbIn->tyenv, st->Ist.LLSC.result);
if (!inLDSO) {
- instrument_mem_access(
- bbOut,
- st->Ist.Store.addr,
- sizeofIRType(typeOfIRExpr(bbIn->tyenv, st->Ist.Store.data)),
- True/*isStore*/,
+ instrument_mem_access(
+ bbOut,
+ st->Ist.LLSC.addr,
+ sizeofIRType(dataTy),
+ False/*!isStore*/,
sizeofIRType(hWordTy)
);
}
+ } else {
+ /* SC */
+ /*ignore */
+ }
+ break;
+ }
+
+ case Ist_Store:
+ /* It seems we pretend that store-conditionals don't
+ exist, viz, just ignore them ... */
+ if (!inLDSO) {
+ instrument_mem_access(
+ bbOut,
+ st->Ist.Store.addr,
+ sizeofIRType(typeOfIRExpr(bbIn->tyenv, st->Ist.Store.data)),
+ True/*isStore*/,
+ sizeofIRType(hWordTy)
+ );
}
break;