commit db5907d7b94ce492f29a96c95e186fdcda23a149
author sewardj <sewardj@a5019735-40e9-0310-863c-91ae7b9d1cf9> Thu Nov 26 17:20:21 2009 +0000
committer sewardj <sewardj@a5019735-40e9-0310-863c-91ae7b9d1cf9> Thu Nov 26 17:20:21 2009 +0000
tree 33e37e60ee917a1822688e2c3d4341f5b158316a
parent 0ca89e0201db387d572047e9afb5d74786370208

Track vex r1930 (Change the IR representation of load linked and store
conditional.)  Completes the fix of #215771.



git-svn-id: svn://svn.valgrind.org/valgrind/trunk@10957 a5019735-40e9-0310-863c-91ae7b9d1cf9

lackey/lk_main.c

diff --git a/lackey/lk_main.c b/lackey/lk_main.c
index d2110b6..39e5bbd 100644
--- a/lackey/lk_main.c
+++ b/lackey/lk_main.c
@@ -790,17 +790,50 @@
                was introduced, since prior to that point, the Vex
                front ends would translate a lock-prefixed instruction
                into a (normal) read followed by a (normal) write. */
+            Int    dataSize;
+            IRType dataTy;
+            IRCAS* cas = st->Ist.CAS.details;
+            tl_assert(cas->addr != NULL);
+            tl_assert(cas->dataLo != NULL);
+            dataTy   = typeOfIRExpr(tyenv, cas->dataLo);
+            dataSize = sizeofIRType(dataTy);
+            if (cas->dataHi != NULL)
+               dataSize *= 2; /* since it's a doubleword-CAS */
             if (clo_trace_mem) {
-               Int    dataSize;
-               IRCAS* cas = st->Ist.CAS.details;
-               tl_assert(cas->addr != NULL);
-               tl_assert(cas->dataLo != NULL);
-               dataSize = sizeofIRType(typeOfIRExpr(tyenv, cas->dataLo));
-               if (cas->dataHi != NULL)
-                  dataSize *= 2; /* since it's a doubleword-CAS */
                addEvent_Dr( sbOut, cas->addr, dataSize );
                addEvent_Dw( sbOut, cas->addr, dataSize );
             }
+            if (clo_detailed_counts) {
+               instrument_detail( sbOut, OpLoad, dataTy );
+               if (cas->dataHi != NULL) /* dcas */
+                  instrument_detail( sbOut, OpLoad, dataTy );
+               instrument_detail( sbOut, OpStore, dataTy );
+               if (cas->dataHi != NULL) /* dcas */
+                  instrument_detail( sbOut, OpStore, dataTy );
+            }
+            addStmtToIRSB( sbOut, st );
+            break;
+         }
+
+         case Ist_LLSC: {
+            IRType dataTy;
+            if (st->Ist.LLSC.storedata == NULL) {
+               /* LL */
+               dataTy = typeOfIRTemp(tyenv, st->Ist.LLSC.result);
+               if (clo_trace_mem)
+                  addEvent_Dr( sbOut, st->Ist.LLSC.addr,
+                                      sizeofIRType(dataTy) );
+               if (clo_detailed_counts)
+                  instrument_detail( sbOut, OpLoad, dataTy );
+            } else {
+               /* SC */
+               dataTy = typeOfIRExpr(tyenv, st->Ist.LLSC.storedata);
+               if (clo_trace_mem)
+                  addEvent_Dw( sbOut, st->Ist.LLSC.addr,
+                                      sizeofIRType(dataTy) );
+               if (clo_detailed_counts)
+                  instrument_detail( sbOut, OpStore, dataTy );
+            }
             addStmtToIRSB( sbOut, st );
             break;
          }
@@ -821,7 +854,8 @@
                                           mkIRExprVec_0() );
                else
                   di = unsafeIRDirty_0_N( 0, "add_one_inverted_Jcc",
-                                          VG_(fnptr_to_fnentry)( &add_one_inverted_Jcc ),
+                                          VG_(fnptr_to_fnentry)(
+                                             &add_one_inverted_Jcc ),
                                           mkIRExprVec_0() );
 
                addStmtToIRSB( sbOut, IRStmt_Dirty(di) );