Merge in branches/DCAS:
This branch adds proper support for atomic instructions, proper in the
sense that the atomicity is preserved through the compilation
pipeline, and thus in the instrumented code.
The change adds a new IR statement kind, IRStmt_CAS, which represents
single- and doubleword compare-and-swap. This is used as the basis
for the translation of all LOCK-prefixed instructions on x86 and
amd64.
The change also extends IRExpr_Load and IRStmt_Store so that
load-linked and store-conditional operations can be represented. This
facilitates correct translation of l[wd]arx and st[wd]cx. on ppc in
the sense that these instructions will now eventually be regenerated
at the end of the compilation pipeline.
git-svn-id: svn://svn.valgrind.org/vex/trunk@1901 8f6e269a-dfd6-0310-a8e1-e2731360e62c
diff --git a/priv/main/vex_main.c b/priv/main/vex_main.c
index 6586304..5a7835f 100644
--- a/priv/main/vex_main.c
+++ b/priv/main/vex_main.c
@@ -744,17 +744,22 @@
| VEX_HWCAPS_X86_SSE2 | VEX_HWCAPS_X86_SSE3))
return "x86-sse1-sse2-sse3";
- return False;
+ return NULL;
}
static HChar* show_hwcaps_amd64 ( UInt hwcaps )
{
- /* Monotonic, SSE3 > baseline. */
- if (hwcaps == 0)
- return "amd64-sse2";
- if (hwcaps == VEX_HWCAPS_AMD64_SSE3)
- return "amd64-sse3";
- return False;
+ /* SSE3 and CX16 are orthogonal and > baseline, although we really
+ don't expect to come across anything which can do SSE3 but can't
+ do CX16. Still, we can handle that case. */
+ const UInt SSE3 = VEX_HWCAPS_AMD64_SSE3;
+ const UInt CX16 = VEX_HWCAPS_AMD64_CX16;
+ UInt c = hwcaps;
+ if (c == 0) return "amd64-sse2";
+ if (c == SSE3) return "amd64-sse3";
+ if (c == CX16) return "amd64-sse2-cx16";
+ if (c == (SSE3|CX16)) return "amd64-sse3-cx16";
+ return NULL;
}
static HChar* show_hwcaps_ppc32 ( UInt hwcaps )