Track the IMark changes in VEX r3055.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@14844 a5019735-40e9-0310-863c-91ae7b9d1cf9
diff --git a/cachegrind/cg_main.c b/cachegrind/cg_main.c
index 685b973..ec9c6e9 100644
--- a/cachegrind/cg_main.c
+++ b/cachegrind/cg_main.c
@@ -1045,9 +1045,10 @@
const VexArchInfo* archinfo_host,
IRType gWordTy, IRType hWordTy )
{
- Int i, isize;
+ Int i;
+ UInt isize;
IRStmt* st;
- Addr64 cia; /* address of current insn */
+ Addr cia; /* address of current insn */
CgState cgs;
IRTypeEnv* tyenv = sbIn->tyenv;
InstrInfo* curr_inode = NULL;
@@ -1242,7 +1243,7 @@
we can pass it to the branch predictor simulation
functions easily. */
Bool inverted;
- Addr64 nia, sea;
+ Addr nia, sea;
IRConst* dst;
IRType tyW = hWordTy;
IROp widen = tyW==Ity_I32 ? Iop_1Uto32 : Iop_1Uto64;
@@ -1257,15 +1258,13 @@
inverted by the ir optimiser. To do that, figure out
the next (fallthrough) instruction's address and the
side exit address and see if they are the same. */
- nia = cia + (Addr64)isize;
- if (tyW == Ity_I32)
- nia &= 0xFFFFFFFFULL;
+ nia = cia + isize;
/* Side exit address */
dst = st->Ist.Exit.dst;
if (tyW == Ity_I32) {
tl_assert(dst->tag == Ico_U32);
- sea = (Addr64)(UInt)dst->Ico.U32;
+ sea = dst->Ico.U32;
} else {
tl_assert(tyW == Ity_I64);
tl_assert(dst->tag == Ico_U64);