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gerrit-public.fairphone.software / platform / external / valgrind / 8e7857747b7e178de4cc825cb35c10efec855ab2 / . / memcheck / mc_machine.c
blob: 429ff4fec7005b70b0b2a2c1d6f5b2e7d95443b5 [file] [log] [blame]
sewardj7cf4e6b2008-05-01 20:24:26 +0000[diff] [blame]1
2/*--------------------------------------------------------------------*/
3/*--- Contains machine-specific (guest-state-layout-specific) ---*/
4/*--- support for origin tracking. ---*/
5/*--- mc_machine.c ---*/
6/*--------------------------------------------------------------------*/
7
8/*
9 This file is part of MemCheck, a heavyweight Valgrind tool for
10 detecting memory errors.
11
sewardj0f157dd2013-10-18 14:27:36 +0000[diff] [blame]12 Copyright (C) 2008-2013 OpenWorks Ltd
sewardj7cf4e6b2008-05-01 20:24:26 +0000[diff] [blame]13 info@open-works.co.uk
14
15 This program is free software; you can redistribute it and/or
16 modify it under the terms of the GNU General Public License as
17 published by the Free Software Foundation; either version 2 of the
18 License, or (at your option) any later version.
19
20 This program is distributed in the hope that it will be useful, but
21 WITHOUT ANY WARRANTY; without even the implied warranty of
22 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
23 General Public License for more details.
24
25 You should have received a copy of the GNU General Public License
26 along with this program; if not, write to the Free Software
27 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
28 02111-1307, USA.
29
30 The GNU General Public License is contained in the file COPYING.
31
32 Neither the names of the U.S. Department of Energy nor the
33 University of California nor the names of its contributors may be
34 used to endorse or promote products derived from this software
35 without prior written permission.
36*/
37
38#include "pub_tool_basics.h"
philippe6643e962012-01-17 21:16:30 +0000[diff] [blame]39#include "pub_tool_poolalloc.h" // For mc_include.h
sewardj7cf4e6b2008-05-01 20:24:26 +0000[diff] [blame]40#include "pub_tool_hashtable.h" // For mc_include.h
41#include "pub_tool_libcassert.h"
42#include "pub_tool_libcprint.h"
43#include "pub_tool_tooliface.h"
floriandea16032014-10-06 21:04:14 +0000[diff] [blame]44#include "pub_tool_guest.h" // VexGuestArchState
sewardj7cf4e6b2008-05-01 20:24:26 +0000[diff] [blame]45
46#include "mc_include.h"
47
floriandea16032014-10-06 21:04:14 +0000[diff] [blame]48#define MC_SIZEOF_GUEST_STATE sizeof(VexGuestArchState)
sewardj7cf4e6b2008-05-01 20:24:26 +0000[diff] [blame]49
petarj4df0bfc2013-02-27 23:17:33 +0000[diff] [blame]50
sewardj7cf4e6b2008-05-01 20:24:26 +0000[diff] [blame]51static inline Bool host_is_big_endian ( void ) {
52 UInt x = 0x11223344;
53 return 0x1122 == *(UShort*)(&x);
54}
55static inline Bool host_is_little_endian ( void ) {
56 UInt x = 0x11223344;
57 return 0x3344 == *(UShort*)(&x);
58}
59
60
61/* Let (offset,szB) describe a reference to the guest state section
62 [offset, offset+szB).
63
64 This function returns the corresponding guest state reference to be
65 used for the origin tag (which of course will be in the second
66 shadow area), or -1 if this piece of guest state is not to be
67 tracked.
68
69 Since origin tags are 32-bits long, we expect any returned value
70 (except -1) to be a multiple of 4, between 0 and
71 sizeof(guest-state)-4 inclusive.
72
73 This is inherently (guest-)architecture specific. For x86 and
74 amd64 we do some somewhat tricky things to give %AH .. %DH their
75 own tags. On ppc32/64 we do some marginally tricky things to give
76 all 16 %CR components their own tags.
77
78 This function only deals with references to the guest state whose
79 offsets are known at translation time (that is, references arising
80 from Put and Get). References whose offset is not known until run
81 time (that is, arise from PutI and GetI) are handled by
82 MC_(get_otrack_reg_array_equiv_int_type) below.
83
84 Note that since some guest state arrays (eg, the x86 FP reg stack)
85 are accessed both as arrays (eg, x87 insns) and directly (eg, MMX
86 insns), the two functions must be consistent for those sections of
87 guest state -- that is, they must both say the area is shadowed, or
88 both say it is not.
89
90 This function is dependent on the host's endianness, hence we
91 assert that the use case is supported.
92*/
93static Int get_otrack_shadow_offset_wrk ( Int offset, Int szB ); /*fwds*/
94
95Int MC_(get_otrack_shadow_offset) ( Int offset, Int szB )
96{
97 Int cand = get_otrack_shadow_offset_wrk( offset, szB );
98 if (cand == -1)
99 return cand;
100 tl_assert(0 == (cand & 3));
101 tl_assert(cand <= MC_SIZEOF_GUEST_STATE-4);
102 return cand;
103}
104
105
106static Int get_otrack_shadow_offset_wrk ( Int offset, Int szB )
107{
108 /* -------------------- ppc64 -------------------- */
109
carllcae0cc22014-08-07 23:17:29 +0000[diff] [blame]110# if defined(VGA_ppc64be) || defined(VGA_ppc64le)
sewardj7cf4e6b2008-05-01 20:24:26 +0000[diff] [blame]111
112# define GOF(_fieldname) \
113 (offsetof(VexGuestPPC64State,guest_##_fieldname))
114# define SZB(_fieldname) \
115 (sizeof(((VexGuestPPC64State*)0)->guest_##_fieldname))
116
117 Int sz = szB;
118 Int o = offset;
119 tl_assert(sz > 0);
sewardj7cf4e6b2008-05-01 20:24:26 +0000[diff] [blame]120
florian17804f62014-09-05 14:49:17 +0000[diff] [blame]121#if defined(VGA_ppc64be)
122 tl_assert(host_is_big_endian());
123#elif defined(VGA_ppc64le)
124 tl_assert(host_is_little_endian());
125#endif
126
sewardj7cf4e6b2008-05-01 20:24:26 +0000[diff] [blame]127 if (sz == 8 || sz == 4) {
128 /* The point of this is to achieve
129 if ((o == GOF(GPRn) && sz == 8) || (o == 4+GOF(GPRn) && sz == 4))
130 return GOF(GPRn);
131 by testing ox instead of o, and setting ox back 4 bytes when sz == 4.
132 */
carll582d5822014-08-07 23:35:54 +0000[diff] [blame]133#if defined(VGA_ppc64le)
134 Int ox = o;
135#else
sewardj85857ab2008-05-06 15:40:32 +0000[diff] [blame]136 Int ox = sz == 8 ? o : (o - 4);
carll582d5822014-08-07 23:35:54 +0000[diff] [blame]137#endif
sewardj7cf4e6b2008-05-01 20:24:26 +0000[diff] [blame]138 if (ox == GOF(GPR0)) return ox;
139 if (ox == GOF(GPR1)) return ox;
140 if (ox == GOF(GPR2)) return ox;
141 if (ox == GOF(GPR3)) return ox;
142 if (ox == GOF(GPR4)) return ox;
143 if (ox == GOF(GPR5)) return ox;
144 if (ox == GOF(GPR6)) return ox;
145 if (ox == GOF(GPR7)) return ox;
146 if (ox == GOF(GPR8)) return ox;
147 if (ox == GOF(GPR9)) return ox;
148 if (ox == GOF(GPR10)) return ox;
149 if (ox == GOF(GPR11)) return ox;
150 if (ox == GOF(GPR12)) return ox;
151 if (ox == GOF(GPR13)) return ox;
152 if (ox == GOF(GPR14)) return ox;
153 if (ox == GOF(GPR15)) return ox;
154 if (ox == GOF(GPR16)) return ox;
155 if (ox == GOF(GPR17)) return ox;
156 if (ox == GOF(GPR18)) return ox;
157 if (ox == GOF(GPR19)) return ox;
158 if (ox == GOF(GPR20)) return ox;
159 if (ox == GOF(GPR21)) return ox;
160 if (ox == GOF(GPR22)) return ox;
161 if (ox == GOF(GPR23)) return ox;
162 if (ox == GOF(GPR24)) return ox;
163 if (ox == GOF(GPR25)) return ox;
164 if (ox == GOF(GPR26)) return ox;
165 if (ox == GOF(GPR27)) return ox;
166 if (ox == GOF(GPR28)) return ox;
167 if (ox == GOF(GPR29)) return ox;
168 if (ox == GOF(GPR30)) return ox;
169 if (ox == GOF(GPR31)) return ox;
170 }
171
172 if (o == GOF(LR) && sz == 8) return o;
173 if (o == GOF(CTR) && sz == 8) return o;
174
175 if (o == GOF(CIA) && sz == 8) return -1;
sewardj71633b12009-03-30 02:27:29 +0000[diff] [blame]176 if (o == GOF(IP_AT_SYSCALL) && sz == 8) return -1; /* slot unused */
sewardjb0ccb4d2012-04-02 10:22:05 +0000[diff] [blame]177 if (o == GOF(FPROUND) && sz == 1) return -1;
178 if (o == GOF(DFPROUND) && sz == 1) return -1;
florian2e497412012-08-26 03:22:09 +0000[diff] [blame]179 if (o == GOF(EMNOTE) && sz == 4) return -1;
sewardj1146ae62014-05-04 10:54:08 +0000[diff] [blame]180 if (o == GOF(CMSTART) && sz == 8) return -1;
181 if (o == GOF(CMLEN) && sz == 8) return -1;
sewardj7cf4e6b2008-05-01 20:24:26 +0000[diff] [blame]182 if (o == GOF(VSCR) && sz == 4) return -1;
183 if (o == GOF(VRSAVE) && sz == 4) return -1;
184 if (o == GOF(REDIR_SP) && sz == 8) return -1;
185
sewardjf34eb492011-04-15 11:57:05 +0000[diff] [blame]186 // With ISA 2.06, the "Vector-Scalar Floating-point" category
187 // provides facilities to support vector and scalar binary floating-
188 // point operations. A unified register file is an integral part
189 // of this new facility, combining floating point and vector registers
190 // using a 64x128-bit vector. These are referred to as VSR[0..63].
191 // The floating point registers are now mapped into double word element 0
192 // of VSR[0..31]. The 32x128-bit vector registers defined by the "Vector
193 // Facility [Category: Vector]" are now mapped to VSR[32..63].
194
195 // Floating point registers . . .
196 if (o == GOF(VSR0) && sz == 8) return o;
197 if (o == GOF(VSR1) && sz == 8) return o;
198 if (o == GOF(VSR2) && sz == 8) return o;
199 if (o == GOF(VSR3) && sz == 8) return o;
200 if (o == GOF(VSR4) && sz == 8) return o;
201 if (o == GOF(VSR5) && sz == 8) return o;
202 if (o == GOF(VSR6) && sz == 8) return o;
203 if (o == GOF(VSR7) && sz == 8) return o;
204 if (o == GOF(VSR8) && sz == 8) return o;
205 if (o == GOF(VSR9) && sz == 8) return o;
206 if (o == GOF(VSR10) && sz == 8) return o;
207 if (o == GOF(VSR11) && sz == 8) return o;
208 if (o == GOF(VSR12) && sz == 8) return o;
209 if (o == GOF(VSR13) && sz == 8) return o;
210 if (o == GOF(VSR14) && sz == 8) return o;
211 if (o == GOF(VSR15) && sz == 8) return o;
212 if (o == GOF(VSR16) && sz == 8) return o;
213 if (o == GOF(VSR17) && sz == 8) return o;
214 if (o == GOF(VSR18) && sz == 8) return o;
215 if (o == GOF(VSR19) && sz == 8) return o;
216 if (o == GOF(VSR20) && sz == 8) return o;
217 if (o == GOF(VSR21) && sz == 8) return o;
218 if (o == GOF(VSR22) && sz == 8) return o;
219 if (o == GOF(VSR23) && sz == 8) return o;
220 if (o == GOF(VSR24) && sz == 8) return o;
221 if (o == GOF(VSR25) && sz == 8) return o;
222 if (o == GOF(VSR26) && sz == 8) return o;
223 if (o == GOF(VSR27) && sz == 8) return o;
224 if (o == GOF(VSR28) && sz == 8) return o;
225 if (o == GOF(VSR29) && sz == 8) return o;
226 if (o == GOF(VSR30) && sz == 8) return o;
227 if (o == GOF(VSR31) && sz == 8) return o;
sewardj7cf4e6b2008-05-01 20:24:26 +0000[diff] [blame]228
229 /* For the various byte sized XER/CR pieces, use offset 8
sewardjf34eb492011-04-15 11:57:05 +0000[diff] [blame]230 in VSR0 .. VSR19. */
231 tl_assert(SZB(VSR0) == 16);
232 if (o == GOF(XER_SO) && sz == 1) return 8 +GOF(VSR0);
233 if (o == GOF(XER_OV) && sz == 1) return 8 +GOF(VSR1);
234 if (o == GOF(XER_CA) && sz == 1) return 8 +GOF(VSR2);
235 if (o == GOF(XER_BC) && sz == 1) return 8 +GOF(VSR3);
sewardj7cf4e6b2008-05-01 20:24:26 +0000[diff] [blame]236
sewardjf34eb492011-04-15 11:57:05 +0000[diff] [blame]237 if (o == GOF(CR0_321) && sz == 1) return 8 +GOF(VSR4);
238 if (o == GOF(CR0_0) && sz == 1) return 8 +GOF(VSR5);
239 if (o == GOF(CR1_321) && sz == 1) return 8 +GOF(VSR6);
240 if (o == GOF(CR1_0) && sz == 1) return 8 +GOF(VSR7);
241 if (o == GOF(CR2_321) && sz == 1) return 8 +GOF(VSR8);
242 if (o == GOF(CR2_0) && sz == 1) return 8 +GOF(VSR9);
243 if (o == GOF(CR3_321) && sz == 1) return 8 +GOF(VSR10);
244 if (o == GOF(CR3_0) && sz == 1) return 8 +GOF(VSR11);
245 if (o == GOF(CR4_321) && sz == 1) return 8 +GOF(VSR12);
246 if (o == GOF(CR4_0) && sz == 1) return 8 +GOF(VSR13);
247 if (o == GOF(CR5_321) && sz == 1) return 8 +GOF(VSR14);
248 if (o == GOF(CR5_0) && sz == 1) return 8 +GOF(VSR15);
249 if (o == GOF(CR6_321) && sz == 1) return 8 +GOF(VSR16);
250 if (o == GOF(CR6_0) && sz == 1) return 8 +GOF(VSR17);
251 if (o == GOF(CR7_321) && sz == 1) return 8 +GOF(VSR18);
252 if (o == GOF(CR7_0) && sz == 1) return 8 +GOF(VSR19);
sewardj7cf4e6b2008-05-01 20:24:26 +0000[diff] [blame]253
sewardjf34eb492011-04-15 11:57:05 +0000[diff] [blame]254 /* Vector registers .. use offset 0 in VSR0 .. VSR63. */
255 if (o >= GOF(VSR0) && o+sz <= GOF(VSR0) +SZB(VSR0)) return 0+ GOF(VSR0);
256 if (o >= GOF(VSR1) && o+sz <= GOF(VSR1) +SZB(VSR1)) return 0+ GOF(VSR1);
257 if (o >= GOF(VSR2) && o+sz <= GOF(VSR2) +SZB(VSR2)) return 0+ GOF(VSR2);
258 if (o >= GOF(VSR3) && o+sz <= GOF(VSR3) +SZB(VSR3)) return 0+ GOF(VSR3);
259 if (o >= GOF(VSR4) && o+sz <= GOF(VSR4) +SZB(VSR4)) return 0+ GOF(VSR4);
260 if (o >= GOF(VSR5) && o+sz <= GOF(VSR5) +SZB(VSR5)) return 0+ GOF(VSR5);
261 if (o >= GOF(VSR6) && o+sz <= GOF(VSR6) +SZB(VSR6)) return 0+ GOF(VSR6);
262 if (o >= GOF(VSR7) && o+sz <= GOF(VSR7) +SZB(VSR7)) return 0+ GOF(VSR7);
263 if (o >= GOF(VSR8) && o+sz <= GOF(VSR8) +SZB(VSR8)) return 0+ GOF(VSR8);
264 if (o >= GOF(VSR9) && o+sz <= GOF(VSR9) +SZB(VSR9)) return 0+ GOF(VSR9);
265 if (o >= GOF(VSR10) && o+sz <= GOF(VSR10)+SZB(VSR10)) return 0+ GOF(VSR10);
266 if (o >= GOF(VSR11) && o+sz <= GOF(VSR11)+SZB(VSR11)) return 0+ GOF(VSR11);
267 if (o >= GOF(VSR12) && o+sz <= GOF(VSR12)+SZB(VSR12)) return 0+ GOF(VSR12);
268 if (o >= GOF(VSR13) && o+sz <= GOF(VSR13)+SZB(VSR13)) return 0+ GOF(VSR13);
269 if (o >= GOF(VSR14) && o+sz <= GOF(VSR14)+SZB(VSR14)) return 0+ GOF(VSR14);
270 if (o >= GOF(VSR15) && o+sz <= GOF(VSR15)+SZB(VSR15)) return 0+ GOF(VSR15);
271 if (o >= GOF(VSR16) && o+sz <= GOF(VSR16)+SZB(VSR16)) return 0+ GOF(VSR16);
272 if (o >= GOF(VSR17) && o+sz <= GOF(VSR17)+SZB(VSR17)) return 0+ GOF(VSR17);
273 if (o >= GOF(VSR18) && o+sz <= GOF(VSR18)+SZB(VSR18)) return 0+ GOF(VSR18);
274 if (o >= GOF(VSR19) && o+sz <= GOF(VSR19)+SZB(VSR19)) return 0+ GOF(VSR19);
275 if (o >= GOF(VSR20) && o+sz <= GOF(VSR20)+SZB(VSR20)) return 0+ GOF(VSR20);
276 if (o >= GOF(VSR21) && o+sz <= GOF(VSR21)+SZB(VSR21)) return 0+ GOF(VSR21);
277 if (o >= GOF(VSR22) && o+sz <= GOF(VSR22)+SZB(VSR22)) return 0+ GOF(VSR22);
278 if (o >= GOF(VSR23) && o+sz <= GOF(VSR23)+SZB(VSR23)) return 0+ GOF(VSR23);
279 if (o >= GOF(VSR24) && o+sz <= GOF(VSR24)+SZB(VSR24)) return 0+ GOF(VSR24);
280 if (o >= GOF(VSR25) && o+sz <= GOF(VSR25)+SZB(VSR25)) return 0+ GOF(VSR25);
281 if (o >= GOF(VSR26) && o+sz <= GOF(VSR26)+SZB(VSR26)) return 0+ GOF(VSR26);
282 if (o >= GOF(VSR27) && o+sz <= GOF(VSR27)+SZB(VSR27)) return 0+ GOF(VSR27);
283 if (o >= GOF(VSR28) && o+sz <= GOF(VSR28)+SZB(VSR28)) return 0+ GOF(VSR28);
284 if (o >= GOF(VSR29) && o+sz <= GOF(VSR29)+SZB(VSR29)) return 0+ GOF(VSR29);
285 if (o >= GOF(VSR30) && o+sz <= GOF(VSR30)+SZB(VSR30)) return 0+ GOF(VSR30);
286 if (o >= GOF(VSR31) && o+sz <= GOF(VSR31)+SZB(VSR31)) return 0+ GOF(VSR31);
287 if (o >= GOF(VSR32) && o+sz <= GOF(VSR32)+SZB(VSR32)) return 0+ GOF(VSR32);
288 if (o >= GOF(VSR33) && o+sz <= GOF(VSR33)+SZB(VSR33)) return 0+ GOF(VSR33);
289 if (o >= GOF(VSR34) && o+sz <= GOF(VSR34)+SZB(VSR34)) return 0+ GOF(VSR34);
290 if (o >= GOF(VSR35) && o+sz <= GOF(VSR35)+SZB(VSR35)) return 0+ GOF(VSR35);
291 if (o >= GOF(VSR36) && o+sz <= GOF(VSR36)+SZB(VSR36)) return 0+ GOF(VSR36);
292 if (o >= GOF(VSR37) && o+sz <= GOF(VSR37)+SZB(VSR37)) return 0+ GOF(VSR37);
293 if (o >= GOF(VSR38) && o+sz <= GOF(VSR38)+SZB(VSR38)) return 0+ GOF(VSR38);
294 if (o >= GOF(VSR39) && o+sz <= GOF(VSR39)+SZB(VSR39)) return 0+ GOF(VSR39);
295 if (o >= GOF(VSR40) && o+sz <= GOF(VSR40)+SZB(VSR40)) return 0+ GOF(VSR40);
296 if (o >= GOF(VSR41) && o+sz <= GOF(VSR41)+SZB(VSR41)) return 0+ GOF(VSR41);
297 if (o >= GOF(VSR42) && o+sz <= GOF(VSR42)+SZB(VSR42)) return 0+ GOF(VSR42);
298 if (o >= GOF(VSR43) && o+sz <= GOF(VSR43)+SZB(VSR43)) return 0+ GOF(VSR43);
299 if (o >= GOF(VSR44) && o+sz <= GOF(VSR44)+SZB(VSR44)) return 0+ GOF(VSR44);
300 if (o >= GOF(VSR45) && o+sz <= GOF(VSR45)+SZB(VSR45)) return 0+ GOF(VSR45);
301 if (o >= GOF(VSR46) && o+sz <= GOF(VSR46)+SZB(VSR46)) return 0+ GOF(VSR46);
302 if (o >= GOF(VSR47) && o+sz <= GOF(VSR47)+SZB(VSR47)) return 0+ GOF(VSR47);
303 if (o >= GOF(VSR48) && o+sz <= GOF(VSR48)+SZB(VSR48)) return 0+ GOF(VSR48);
304 if (o >= GOF(VSR49) && o+sz <= GOF(VSR49)+SZB(VSR49)) return 0+ GOF(VSR49);
305 if (o >= GOF(VSR50) && o+sz <= GOF(VSR50)+SZB(VSR50)) return 0+ GOF(VSR50);
306 if (o >= GOF(VSR51) && o+sz <= GOF(VSR51)+SZB(VSR51)) return 0+ GOF(VSR51);
307 if (o >= GOF(VSR52) && o+sz <= GOF(VSR52)+SZB(VSR52)) return 0+ GOF(VSR52);
308 if (o >= GOF(VSR53) && o+sz <= GOF(VSR53)+SZB(VSR53)) return 0+ GOF(VSR53);
309 if (o >= GOF(VSR54) && o+sz <= GOF(VSR54)+SZB(VSR54)) return 0+ GOF(VSR54);
310 if (o >= GOF(VSR55) && o+sz <= GOF(VSR55)+SZB(VSR55)) return 0+ GOF(VSR55);
311 if (o >= GOF(VSR56) && o+sz <= GOF(VSR56)+SZB(VSR56)) return 0+ GOF(VSR56);
312 if (o >= GOF(VSR57) && o+sz <= GOF(VSR57)+SZB(VSR57)) return 0+ GOF(VSR57);
313 if (o >= GOF(VSR58) && o+sz <= GOF(VSR58)+SZB(VSR58)) return 0+ GOF(VSR58);
314 if (o >= GOF(VSR59) && o+sz <= GOF(VSR59)+SZB(VSR59)) return 0+ GOF(VSR59);
315 if (o >= GOF(VSR60) && o+sz <= GOF(VSR60)+SZB(VSR60)) return 0+ GOF(VSR60);
316 if (o >= GOF(VSR61) && o+sz <= GOF(VSR61)+SZB(VSR61)) return 0+ GOF(VSR61);
317 if (o >= GOF(VSR62) && o+sz <= GOF(VSR62)+SZB(VSR62)) return 0+ GOF(VSR62);
318 if (o >= GOF(VSR63) && o+sz <= GOF(VSR63)+SZB(VSR63)) return 0+ GOF(VSR63);
sewardj7cf4e6b2008-05-01 20:24:26 +0000[diff] [blame]319
320 VG_(printf)("MC_(get_otrack_shadow_offset)(ppc64)(off=%d,sz=%d)\n",
321 offset,szB);
322 tl_assert(0);
323# undef GOF
324# undef SZB
325
326 /* -------------------- ppc32 -------------------- */
327
328# elif defined(VGA_ppc32)
329
330# define GOF(_fieldname) \
331 (offsetof(VexGuestPPC32State,guest_##_fieldname))
332# define SZB(_fieldname) \
333 (sizeof(((VexGuestPPC32State*)0)->guest_##_fieldname))
334 Int o = offset;
335 Int sz = szB;
336 tl_assert(sz > 0);
sewardj7cf4e6b2008-05-01 20:24:26 +0000[diff] [blame]337
338 if (o == GOF(GPR0) && sz == 4) return o;
339 if (o == GOF(GPR1) && sz == 4) return o;
340 if (o == GOF(GPR2) && sz == 4) return o;
341 if (o == GOF(GPR3) && sz == 4) return o;
342 if (o == GOF(GPR4) && sz == 4) return o;
343 if (o == GOF(GPR5) && sz == 4) return o;
344 if (o == GOF(GPR6) && sz == 4) return o;
345 if (o == GOF(GPR7) && sz == 4) return o;
346 if (o == GOF(GPR8) && sz == 4) return o;
347 if (o == GOF(GPR9) && sz == 4) return o;
348 if (o == GOF(GPR10) && sz == 4) return o;
349 if (o == GOF(GPR11) && sz == 4) return o;
350 if (o == GOF(GPR12) && sz == 4) return o;
351 if (o == GOF(GPR13) && sz == 4) return o;
352 if (o == GOF(GPR14) && sz == 4) return o;
353 if (o == GOF(GPR15) && sz == 4) return o;
354 if (o == GOF(GPR16) && sz == 4) return o;
355 if (o == GOF(GPR17) && sz == 4) return o;
356 if (o == GOF(GPR18) && sz == 4) return o;
357 if (o == GOF(GPR19) && sz == 4) return o;
358 if (o == GOF(GPR20) && sz == 4) return o;
359 if (o == GOF(GPR21) && sz == 4) return o;
360 if (o == GOF(GPR22) && sz == 4) return o;
361 if (o == GOF(GPR23) && sz == 4) return o;
362 if (o == GOF(GPR24) && sz == 4) return o;
363 if (o == GOF(GPR25) && sz == 4) return o;
364 if (o == GOF(GPR26) && sz == 4) return o;
365 if (o == GOF(GPR27) && sz == 4) return o;
366 if (o == GOF(GPR28) && sz == 4) return o;
367 if (o == GOF(GPR29) && sz == 4) return o;
368 if (o == GOF(GPR30) && sz == 4) return o;
369 if (o == GOF(GPR31) && sz == 4) return o;
370
371 if (o == GOF(LR) && sz == 4) return o;
372 if (o == GOF(CTR) && sz == 4) return o;
373
374 if (o == GOF(CIA) && sz == 4) return -1;
sewardj71633b12009-03-30 02:27:29 +0000[diff] [blame]375 if (o == GOF(IP_AT_SYSCALL) && sz == 4) return -1; /* slot unused */
sewardjf06eabf2012-04-02 15:10:37 +0000[diff] [blame]376 if (o == GOF(FPROUND) && sz == 1) return -1;
377 if (o == GOF(DFPROUND) && sz == 1) return -1;
sewardj3b507352009-02-14 15:28:46 +0000[diff] [blame]378 if (o == GOF(VRSAVE) && sz == 4) return -1;
florian2e497412012-08-26 03:22:09 +0000[diff] [blame]379 if (o == GOF(EMNOTE) && sz == 4) return -1;
sewardj1146ae62014-05-04 10:54:08 +0000[diff] [blame]380 if (o == GOF(CMSTART) && sz == 4) return -1;
381 if (o == GOF(CMLEN) && sz == 4) return -1;
sewardj7cf4e6b2008-05-01 20:24:26 +0000[diff] [blame]382 if (o == GOF(VSCR) && sz == 4) return -1;
383 if (o == GOF(REDIR_SP) && sz == 4) return -1;
384 if (o == GOF(SPRG3_RO) && sz == 4) return -1;
385
sewardjf34eb492011-04-15 11:57:05 +0000[diff] [blame]386 // With ISA 2.06, the "Vector-Scalar Floating-point" category
387 // provides facilities to support vector and scalar binary floating-
388 // point operations. A unified register file is an integral part
389 // of this new facility, combining floating point and vector registers
390 // using a 64x128-bit vector. These are referred to as VSR[0..63].
391 // The floating point registers are now mapped into double word element 0
392 // of VSR[0..31]. The 32x128-bit vector registers defined by the "Vector
393 // Facility [Category: Vector]" are now mapped to VSR[32..63].
394
395 // Floating point registers . . .
396 if (o == GOF(VSR0) && sz == 8) return o;
397 if (o == GOF(VSR1) && sz == 8) return o;
398 if (o == GOF(VSR2) && sz == 8) return o;
399 if (o == GOF(VSR3) && sz == 8) return o;
400 if (o == GOF(VSR4) && sz == 8) return o;
401 if (o == GOF(VSR5) && sz == 8) return o;
402 if (o == GOF(VSR6) && sz == 8) return o;
403 if (o == GOF(VSR7) && sz == 8) return o;
404 if (o == GOF(VSR8) && sz == 8) return o;
405 if (o == GOF(VSR9) && sz == 8) return o;
406 if (o == GOF(VSR10) && sz == 8) return o;
407 if (o == GOF(VSR11) && sz == 8) return o;
408 if (o == GOF(VSR12) && sz == 8) return o;
409 if (o == GOF(VSR13) && sz == 8) return o;
410 if (o == GOF(VSR14) && sz == 8) return o;
411 if (o == GOF(VSR15) && sz == 8) return o;
412 if (o == GOF(VSR16) && sz == 8) return o;
413 if (o == GOF(VSR17) && sz == 8) return o;
414 if (o == GOF(VSR18) && sz == 8) return o;
415 if (o == GOF(VSR19) && sz == 8) return o;
416 if (o == GOF(VSR20) && sz == 8) return o;
417 if (o == GOF(VSR21) && sz == 8) return o;
418 if (o == GOF(VSR22) && sz == 8) return o;
419 if (o == GOF(VSR23) && sz == 8) return o;
420 if (o == GOF(VSR24) && sz == 8) return o;
421 if (o == GOF(VSR25) && sz == 8) return o;
422 if (o == GOF(VSR26) && sz == 8) return o;
423 if (o == GOF(VSR27) && sz == 8) return o;
424 if (o == GOF(VSR28) && sz == 8) return o;
425 if (o == GOF(VSR29) && sz == 8) return o;
426 if (o == GOF(VSR30) && sz == 8) return o;
427 if (o == GOF(VSR31) && sz == 8) return o;
sewardj7cf4e6b2008-05-01 20:24:26 +0000[diff] [blame]428
429 /* For the various byte sized XER/CR pieces, use offset 8
sewardjf34eb492011-04-15 11:57:05 +0000[diff] [blame]430 in VSR0 .. VSR19. */
431 tl_assert(SZB(VSR0) == 16);
432 if (o == GOF(XER_SO) && sz == 1) return 8 +GOF(VSR0);
433 if (o == GOF(XER_OV) && sz == 1) return 8 +GOF(VSR1);
434 if (o == GOF(XER_CA) && sz == 1) return 8 +GOF(VSR2);
435 if (o == GOF(XER_BC) && sz == 1) return 8 +GOF(VSR3);
sewardj7cf4e6b2008-05-01 20:24:26 +0000[diff] [blame]436
sewardjf34eb492011-04-15 11:57:05 +0000[diff] [blame]437 if (o == GOF(CR0_321) && sz == 1) return 8 +GOF(VSR4);
438 if (o == GOF(CR0_0) && sz == 1) return 8 +GOF(VSR5);
439 if (o == GOF(CR1_321) && sz == 1) return 8 +GOF(VSR6);
440 if (o == GOF(CR1_0) && sz == 1) return 8 +GOF(VSR7);
441 if (o == GOF(CR2_321) && sz == 1) return 8 +GOF(VSR8);
442 if (o == GOF(CR2_0) && sz == 1) return 8 +GOF(VSR9);
443 if (o == GOF(CR3_321) && sz == 1) return 8 +GOF(VSR10);
444 if (o == GOF(CR3_0) && sz == 1) return 8 +GOF(VSR11);
445 if (o == GOF(CR4_321) && sz == 1) return 8 +GOF(VSR12);
446 if (o == GOF(CR4_0) && sz == 1) return 8 +GOF(VSR13);
447 if (o == GOF(CR5_321) && sz == 1) return 8 +GOF(VSR14);
448 if (o == GOF(CR5_0) && sz == 1) return 8 +GOF(VSR15);
449 if (o == GOF(CR6_321) && sz == 1) return 8 +GOF(VSR16);
450 if (o == GOF(CR6_0) && sz == 1) return 8 +GOF(VSR17);
451 if (o == GOF(CR7_321) && sz == 1) return 8 +GOF(VSR18);
452 if (o == GOF(CR7_0) && sz == 1) return 8 +GOF(VSR19);
sewardj7cf4e6b2008-05-01 20:24:26 +0000[diff] [blame]453
sewardjf34eb492011-04-15 11:57:05 +0000[diff] [blame]454 /* Vector registers .. use offset 0 in VSR0 .. VSR63. */
455 if (o >= GOF(VSR0) && o+sz <= GOF(VSR0) +SZB(VSR0)) return 0+ GOF(VSR0);
456 if (o >= GOF(VSR1) && o+sz <= GOF(VSR1) +SZB(VSR1)) return 0+ GOF(VSR1);
457 if (o >= GOF(VSR2) && o+sz <= GOF(VSR2) +SZB(VSR2)) return 0+ GOF(VSR2);
458 if (o >= GOF(VSR3) && o+sz <= GOF(VSR3) +SZB(VSR3)) return 0+ GOF(VSR3);
459 if (o >= GOF(VSR4) && o+sz <= GOF(VSR4) +SZB(VSR4)) return 0+ GOF(VSR4);
460 if (o >= GOF(VSR5) && o+sz <= GOF(VSR5) +SZB(VSR5)) return 0+ GOF(VSR5);
461 if (o >= GOF(VSR6) && o+sz <= GOF(VSR6) +SZB(VSR6)) return 0+ GOF(VSR6);
462 if (o >= GOF(VSR7) && o+sz <= GOF(VSR7) +SZB(VSR7)) return 0+ GOF(VSR7);
463 if (o >= GOF(VSR8) && o+sz <= GOF(VSR8) +SZB(VSR8)) return 0+ GOF(VSR8);
464 if (o >= GOF(VSR9) && o+sz <= GOF(VSR9) +SZB(VSR9)) return 0+ GOF(VSR9);
465 if (o >= GOF(VSR10) && o+sz <= GOF(VSR10)+SZB(VSR10)) return 0+ GOF(VSR10);
466 if (o >= GOF(VSR11) && o+sz <= GOF(VSR11)+SZB(VSR11)) return 0+ GOF(VSR11);
467 if (o >= GOF(VSR12) && o+sz <= GOF(VSR12)+SZB(VSR12)) return 0+ GOF(VSR12);
468 if (o >= GOF(VSR13) && o+sz <= GOF(VSR13)+SZB(VSR13)) return 0+ GOF(VSR13);
469 if (o >= GOF(VSR14) && o+sz <= GOF(VSR14)+SZB(VSR14)) return 0+ GOF(VSR14);
470 if (o >= GOF(VSR15) && o+sz <= GOF(VSR15)+SZB(VSR15)) return 0+ GOF(VSR15);
471 if (o >= GOF(VSR16) && o+sz <= GOF(VSR16)+SZB(VSR16)) return 0+ GOF(VSR16);
472 if (o >= GOF(VSR17) && o+sz <= GOF(VSR17)+SZB(VSR17)) return 0+ GOF(VSR17);
473 if (o >= GOF(VSR18) && o+sz <= GOF(VSR18)+SZB(VSR18)) return 0+ GOF(VSR18);
474 if (o >= GOF(VSR19) && o+sz <= GOF(VSR19)+SZB(VSR19)) return 0+ GOF(VSR19);
475 if (o >= GOF(VSR20) && o+sz <= GOF(VSR20)+SZB(VSR20)) return 0+ GOF(VSR20);
476 if (o >= GOF(VSR21) && o+sz <= GOF(VSR21)+SZB(VSR21)) return 0+ GOF(VSR21);
477 if (o >= GOF(VSR22) && o+sz <= GOF(VSR22)+SZB(VSR22)) return 0+ GOF(VSR22);
478 if (o >= GOF(VSR23) && o+sz <= GOF(VSR23)+SZB(VSR23)) return 0+ GOF(VSR23);
479 if (o >= GOF(VSR24) && o+sz <= GOF(VSR24)+SZB(VSR24)) return 0+ GOF(VSR24);
480 if (o >= GOF(VSR25) && o+sz <= GOF(VSR25)+SZB(VSR25)) return 0+ GOF(VSR25);
481 if (o >= GOF(VSR26) && o+sz <= GOF(VSR26)+SZB(VSR26)) return 0+ GOF(VSR26);
482 if (o >= GOF(VSR27) && o+sz <= GOF(VSR27)+SZB(VSR27)) return 0+ GOF(VSR27);
483 if (o >= GOF(VSR28) && o+sz <= GOF(VSR28)+SZB(VSR28)) return 0+ GOF(VSR28);
484 if (o >= GOF(VSR29) && o+sz <= GOF(VSR29)+SZB(VSR29)) return 0+ GOF(VSR29);
485 if (o >= GOF(VSR30) && o+sz <= GOF(VSR30)+SZB(VSR30)) return 0+ GOF(VSR30);
486 if (o >= GOF(VSR31) && o+sz <= GOF(VSR31)+SZB(VSR31)) return 0+ GOF(VSR31);
487 if (o >= GOF(VSR32) && o+sz <= GOF(VSR32)+SZB(VSR32)) return 0+ GOF(VSR32);
488 if (o >= GOF(VSR33) && o+sz <= GOF(VSR33)+SZB(VSR33)) return 0+ GOF(VSR33);
489 if (o >= GOF(VSR34) && o+sz <= GOF(VSR34)+SZB(VSR34)) return 0+ GOF(VSR34);
490 if (o >= GOF(VSR35) && o+sz <= GOF(VSR35)+SZB(VSR35)) return 0+ GOF(VSR35);
491 if (o >= GOF(VSR36) && o+sz <= GOF(VSR36)+SZB(VSR36)) return 0+ GOF(VSR36);
492 if (o >= GOF(VSR37) && o+sz <= GOF(VSR37)+SZB(VSR37)) return 0+ GOF(VSR37);
493 if (o >= GOF(VSR38) && o+sz <= GOF(VSR38)+SZB(VSR38)) return 0+ GOF(VSR38);
494 if (o >= GOF(VSR39) && o+sz <= GOF(VSR39)+SZB(VSR39)) return 0+ GOF(VSR39);
495 if (o >= GOF(VSR40) && o+sz <= GOF(VSR40)+SZB(VSR40)) return 0+ GOF(VSR40);
496 if (o >= GOF(VSR41) && o+sz <= GOF(VSR41)+SZB(VSR41)) return 0+ GOF(VSR41);
497 if (o >= GOF(VSR42) && o+sz <= GOF(VSR42)+SZB(VSR42)) return 0+ GOF(VSR42);
498 if (o >= GOF(VSR43) && o+sz <= GOF(VSR43)+SZB(VSR43)) return 0+ GOF(VSR43);
499 if (o >= GOF(VSR44) && o+sz <= GOF(VSR44)+SZB(VSR44)) return 0+ GOF(VSR44);
500 if (o >= GOF(VSR45) && o+sz <= GOF(VSR45)+SZB(VSR45)) return 0+ GOF(VSR45);
501 if (o >= GOF(VSR46) && o+sz <= GOF(VSR46)+SZB(VSR46)) return 0+ GOF(VSR46);
502 if (o >= GOF(VSR47) && o+sz <= GOF(VSR47)+SZB(VSR47)) return 0+ GOF(VSR47);
503 if (o >= GOF(VSR48) && o+sz <= GOF(VSR48)+SZB(VSR48)) return 0+ GOF(VSR48);
504 if (o >= GOF(VSR49) && o+sz <= GOF(VSR49)+SZB(VSR49)) return 0+ GOF(VSR49);
505 if (o >= GOF(VSR50) && o+sz <= GOF(VSR50)+SZB(VSR50)) return 0+ GOF(VSR50);
506 if (o >= GOF(VSR51) && o+sz <= GOF(VSR51)+SZB(VSR51)) return 0+ GOF(VSR51);
507 if (o >= GOF(VSR52) && o+sz <= GOF(VSR52)+SZB(VSR52)) return 0+ GOF(VSR52);
508 if (o >= GOF(VSR53) && o+sz <= GOF(VSR53)+SZB(VSR53)) return 0+ GOF(VSR53);
509 if (o >= GOF(VSR54) && o+sz <= GOF(VSR54)+SZB(VSR54)) return 0+ GOF(VSR54);
510 if (o >= GOF(VSR55) && o+sz <= GOF(VSR55)+SZB(VSR55)) return 0+ GOF(VSR55);
511 if (o >= GOF(VSR56) && o+sz <= GOF(VSR56)+SZB(VSR56)) return 0+ GOF(VSR56);
512 if (o >= GOF(VSR57) && o+sz <= GOF(VSR57)+SZB(VSR57)) return 0+ GOF(VSR57);
513 if (o >= GOF(VSR58) && o+sz <= GOF(VSR58)+SZB(VSR58)) return 0+ GOF(VSR58);
514 if (o >= GOF(VSR59) && o+sz <= GOF(VSR59)+SZB(VSR59)) return 0+ GOF(VSR59);
515 if (o >= GOF(VSR60) && o+sz <= GOF(VSR60)+SZB(VSR60)) return 0+ GOF(VSR60);
516 if (o >= GOF(VSR61) && o+sz <= GOF(VSR61)+SZB(VSR61)) return 0+ GOF(VSR61);
517 if (o >= GOF(VSR62) && o+sz <= GOF(VSR62)+SZB(VSR62)) return 0+ GOF(VSR62);
518 if (o >= GOF(VSR63) && o+sz <= GOF(VSR63)+SZB(VSR63)) return 0+ GOF(VSR63);
sewardj7cf4e6b2008-05-01 20:24:26 +0000[diff] [blame]519
520 VG_(printf)("MC_(get_otrack_shadow_offset)(ppc32)(off=%d,sz=%d)\n",
521 offset,szB);
522 tl_assert(0);
523# undef GOF
524# undef SZB
525
526 /* -------------------- amd64 -------------------- */
527
528# elif defined(VGA_amd64)
529
530# define GOF(_fieldname) \
531 (offsetof(VexGuestAMD64State,guest_##_fieldname))
532# define SZB(_fieldname) \
533 (sizeof(((VexGuestAMD64State*)0)->guest_##_fieldname))
534 Int o = offset;
535 Int sz = szB;
536 Bool is1248 = sz == 8 || sz == 4 || sz == 2 || sz == 1;
537 tl_assert(sz > 0);
538 tl_assert(host_is_little_endian());
539
540 if (o == GOF(RAX) && is1248) return o;
541 if (o == GOF(RCX) && is1248) return o;
542 if (o == GOF(RDX) && is1248) return o;
543 if (o == GOF(RBX) && is1248) return o;
544 if (o == GOF(RSP) && is1248) return o;
545 if (o == GOF(RBP) && is1248) return o;
546 if (o == GOF(RSI) && is1248) return o;
547 if (o == GOF(RDI) && is1248) return o;
548 if (o == GOF(R8) && is1248) return o;
549 if (o == GOF(R9) && is1248) return o;
550 if (o == GOF(R10) && is1248) return o;
551 if (o == GOF(R11) && is1248) return o;
552 if (o == GOF(R12) && is1248) return o;
553 if (o == GOF(R13) && is1248) return o;
554 if (o == GOF(R14) && is1248) return o;
555 if (o == GOF(R15) && is1248) return o;
556
557 if (o == GOF(CC_DEP1) && sz == 8) return o;
558 if (o == GOF(CC_DEP2) && sz == 8) return o;
559
560 if (o == GOF(CC_OP) && sz == 8) return -1; /* slot used for %AH */
561 if (o == GOF(CC_NDEP) && sz == 8) return -1; /* slot used for %BH */
562 if (o == GOF(DFLAG) && sz == 8) return -1; /* slot used for %CH */
563 if (o == GOF(RIP) && sz == 8) return -1; /* slot unused */
sewardj71633b12009-03-30 02:27:29 +0000[diff] [blame]564 if (o == GOF(IP_AT_SYSCALL) && sz == 8) return -1; /* slot unused */
sewardj7cf4e6b2008-05-01 20:24:26 +0000[diff] [blame]565 if (o == GOF(IDFLAG) && sz == 8) return -1; /* slot used for %DH */
sewardj65864932010-09-28 16:00:11 +0000[diff] [blame]566 if (o == GOF(ACFLAG) && sz == 8) return -1; /* slot unused */
philippe8e785772014-12-17 00:00:11 +0000[diff] [blame^]567 if (o == GOF(FS_CONST) && sz == 8) return -1; /* slot unused */
568 if (o == GOF(GS_CONST) && sz == 8) return -1; /* slot unused */
sewardj1146ae62014-05-04 10:54:08 +0000[diff] [blame]569 if (o == GOF(CMSTART) && sz == 8) return -1; /* slot unused */
570 if (o == GOF(CMLEN) && sz == 8) return -1; /* slot unused */
sewardj3d5246f2013-01-29 21:13:00 +0000[diff] [blame]571 if (o == GOF(NRADDR) && sz == 8) return -1; /* slot unused */
sewardj7cf4e6b2008-05-01 20:24:26 +0000[diff] [blame]572
573 /* Treat %AH, %BH, %CH, %DH as independent registers. To do this
574 requires finding 4 unused 32-bit slots in the second-shadow
575 guest state, respectively: CC_OP CC_NDEP DFLAG IDFLAG, since
576 none of those are tracked. */
577 tl_assert(SZB(CC_OP) == 8);
578 tl_assert(SZB(CC_NDEP) == 8);
579 tl_assert(SZB(IDFLAG) == 8);
580 tl_assert(SZB(DFLAG) == 8);
581
582 if (o == 1+ GOF(RAX) && szB == 1) return GOF(CC_OP);
583 if (o == 1+ GOF(RBX) && szB == 1) return GOF(CC_NDEP);
584 if (o == 1+ GOF(RCX) && szB == 1) return GOF(DFLAG);
585 if (o == 1+ GOF(RDX) && szB == 1) return GOF(IDFLAG);
586
587 /* skip XMM and FP admin stuff */
588 if (o == GOF(SSEROUND) && szB == 8) return -1;
589 if (o == GOF(FTOP) && szB == 4) return -1;
590 if (o == GOF(FPROUND) && szB == 8) return -1;
florian2e497412012-08-26 03:22:09 +0000[diff] [blame]591 if (o == GOF(EMNOTE) && szB == 4) return -1;
sewardj89ea7ab2008-05-27 16:08:24 +0000[diff] [blame]592 if (o == GOF(FC3210) && szB == 8) return -1;
sewardj7cf4e6b2008-05-01 20:24:26 +0000[diff] [blame]593
594 /* XMM registers */
sewardj45fa9f42012-05-21 10:18:10 +0000[diff] [blame]595 if (o >= GOF(YMM0) && o+sz <= GOF(YMM0) +SZB(YMM0)) return GOF(YMM0);
596 if (o >= GOF(YMM1) && o+sz <= GOF(YMM1) +SZB(YMM1)) return GOF(YMM1);
597 if (o >= GOF(YMM2) && o+sz <= GOF(YMM2) +SZB(YMM2)) return GOF(YMM2);
598 if (o >= GOF(YMM3) && o+sz <= GOF(YMM3) +SZB(YMM3)) return GOF(YMM3);
599 if (o >= GOF(YMM4) && o+sz <= GOF(YMM4) +SZB(YMM4)) return GOF(YMM4);
600 if (o >= GOF(YMM5) && o+sz <= GOF(YMM5) +SZB(YMM5)) return GOF(YMM5);
601 if (o >= GOF(YMM6) && o+sz <= GOF(YMM6) +SZB(YMM6)) return GOF(YMM6);
602 if (o >= GOF(YMM7) && o+sz <= GOF(YMM7) +SZB(YMM7)) return GOF(YMM7);
603 if (o >= GOF(YMM8) && o+sz <= GOF(YMM8) +SZB(YMM8)) return GOF(YMM8);
604 if (o >= GOF(YMM9) && o+sz <= GOF(YMM9) +SZB(YMM9)) return GOF(YMM9);
605 if (o >= GOF(YMM10) && o+sz <= GOF(YMM10)+SZB(YMM10)) return GOF(YMM10);
606 if (o >= GOF(YMM11) && o+sz <= GOF(YMM11)+SZB(YMM11)) return GOF(YMM11);
607 if (o >= GOF(YMM12) && o+sz <= GOF(YMM12)+SZB(YMM12)) return GOF(YMM12);
608 if (o >= GOF(YMM13) && o+sz <= GOF(YMM13)+SZB(YMM13)) return GOF(YMM13);
609 if (o >= GOF(YMM14) && o+sz <= GOF(YMM14)+SZB(YMM14)) return GOF(YMM14);
610 if (o >= GOF(YMM15) && o+sz <= GOF(YMM15)+SZB(YMM15)) return GOF(YMM15);
611 if (o >= GOF(YMM16) && o+sz <= GOF(YMM16)+SZB(YMM16)) return GOF(YMM16);
sewardj7cf4e6b2008-05-01 20:24:26 +0000[diff] [blame]612
sewardjf1a483a2008-06-13 07:44:02 +0000[diff] [blame]613 /* MMX accesses to FP regs. Need to allow for 32-bit references
614 due to dirty helpers for frstor etc, which reference the entire
615 64-byte block in one go. */
616 if (o >= GOF(FPREG[0])
617 && o+sz <= GOF(FPREG[0])+SZB(FPREG[0])) return GOF(FPREG[0]);
618 if (o >= GOF(FPREG[1])
619 && o+sz <= GOF(FPREG[1])+SZB(FPREG[1])) return GOF(FPREG[1]);
620 if (o >= GOF(FPREG[2])
621 && o+sz <= GOF(FPREG[2])+SZB(FPREG[2])) return GOF(FPREG[2]);
622 if (o >= GOF(FPREG[3])
623 && o+sz <= GOF(FPREG[3])+SZB(FPREG[3])) return GOF(FPREG[3]);
624 if (o >= GOF(FPREG[4])
625 && o+sz <= GOF(FPREG[4])+SZB(FPREG[4])) return GOF(FPREG[4]);
626 if (o >= GOF(FPREG[5])
627 && o+sz <= GOF(FPREG[5])+SZB(FPREG[5])) return GOF(FPREG[5]);
628 if (o >= GOF(FPREG[6])
629 && o+sz <= GOF(FPREG[6])+SZB(FPREG[6])) return GOF(FPREG[6]);
630 if (o >= GOF(FPREG[7])
631 && o+sz <= GOF(FPREG[7])+SZB(FPREG[7])) return GOF(FPREG[7]);
sewardj7cf4e6b2008-05-01 20:24:26 +0000[diff] [blame]632
633 /* Map high halves of %RAX,%RCX,%RDX,%RBX to the whole register.
634 This is needed because the general handling of dirty helper
635 calls is done in 4 byte chunks. Hence we will see these.
636 Currently we only expect to see artefacts from CPUID. */
637 if (o == 4+ GOF(RAX) && sz == 4) return GOF(RAX);
638 if (o == 4+ GOF(RCX) && sz == 4) return GOF(RCX);
639 if (o == 4+ GOF(RDX) && sz == 4) return GOF(RDX);
640 if (o == 4+ GOF(RBX) && sz == 4) return GOF(RBX);
641
642 VG_(printf)("MC_(get_otrack_shadow_offset)(amd64)(off=%d,sz=%d)\n",
643 offset,szB);
644 tl_assert(0);
645# undef GOF
646# undef SZB
647
648 /* --------------------- x86 --------------------- */
649
650# elif defined(VGA_x86)
651
652# define GOF(_fieldname) \
653 (offsetof(VexGuestX86State,guest_##_fieldname))
654# define SZB(_fieldname) \
655 (sizeof(((VexGuestX86State*)0)->guest_##_fieldname))
656
657 Int o = offset;
658 Int sz = szB;
659 Bool is124 = sz == 4 || sz == 2 || sz == 1;
660 tl_assert(sz > 0);
661 tl_assert(host_is_little_endian());
662
663 if (o == GOF(EAX) && is124) return o;
664 if (o == GOF(ECX) && is124) return o;
665 if (o == GOF(EDX) && is124) return o;
666 if (o == GOF(EBX) && is124) return o;
667 if (o == GOF(ESP) && is124) return o;
668 if (o == GOF(EBP) && is124) return o;
669 if (o == GOF(ESI) && is124) return o;
670 if (o == GOF(EDI) && is124) return o;
671
672 if (o == GOF(CC_DEP1) && sz == 4) return o;
673 if (o == GOF(CC_DEP2) && sz == 4) return o;
674
675 if (o == GOF(CC_OP) && sz == 4) return -1; /* slot used for %AH */
676 if (o == GOF(CC_NDEP) && sz == 4) return -1; /* slot used for %BH */
677 if (o == GOF(DFLAG) && sz == 4) return -1; /* slot used for %CH */
678 if (o == GOF(EIP) && sz == 4) return -1; /* slot unused */
sewardj71633b12009-03-30 02:27:29 +0000[diff] [blame]679 if (o == GOF(IP_AT_SYSCALL) && sz == 4) return -1; /* slot unused */
sewardj7cf4e6b2008-05-01 20:24:26 +0000[diff] [blame]680 if (o == GOF(IDFLAG) && sz == 4) return -1; /* slot used for %DH */
681 if (o == GOF(ACFLAG) && sz == 4) return -1; /* slot unused */
sewardj1146ae62014-05-04 10:54:08 +0000[diff] [blame]682 if (o == GOF(CMSTART) && sz == 4) return -1; /* slot unused */
683 if (o == GOF(CMLEN) && sz == 4) return -1; /* slot unused */
sewardj5575f052011-01-28 00:53:37 +0000[diff] [blame]684 if (o == GOF(NRADDR) && sz == 4) return -1; /* slot unused */
sewardj7cf4e6b2008-05-01 20:24:26 +0000[diff] [blame]685
686 /* Treat %AH, %BH, %CH, %DH as independent registers. To do this
687 requires finding 4 unused 32-bit slots in the second-shadow
688 guest state, respectively: CC_OP CC_NDEP DFLAG IDFLAG since none
689 of those are tracked. */
690 tl_assert(SZB(CC_OP) == 4);
691 tl_assert(SZB(CC_NDEP) == 4);
692 tl_assert(SZB(DFLAG) == 4);
693 tl_assert(SZB(IDFLAG) == 4);
694 if (o == 1+ GOF(EAX) && szB == 1) return GOF(CC_OP);
695 if (o == 1+ GOF(EBX) && szB == 1) return GOF(CC_NDEP);
696 if (o == 1+ GOF(ECX) && szB == 1) return GOF(DFLAG);
697 if (o == 1+ GOF(EDX) && szB == 1) return GOF(IDFLAG);
698
699 /* skip XMM and FP admin stuff */
700 if (o == GOF(SSEROUND) && szB == 4) return -1;
701 if (o == GOF(FTOP) && szB == 4) return -1;
702 if (o == GOF(FPROUND) && szB == 4) return -1;
florian2e497412012-08-26 03:22:09 +0000[diff] [blame]703 if (o == GOF(EMNOTE) && szB == 4) return -1;
sewardj7cf4e6b2008-05-01 20:24:26 +0000[diff] [blame]704 if (o == GOF(FC3210) && szB == 4) return -1;
705
706 /* XMM registers */
707 if (o >= GOF(XMM0) && o+sz <= GOF(XMM0)+SZB(XMM0)) return GOF(XMM0);
708 if (o >= GOF(XMM1) && o+sz <= GOF(XMM1)+SZB(XMM1)) return GOF(XMM1);
709 if (o >= GOF(XMM2) && o+sz <= GOF(XMM2)+SZB(XMM2)) return GOF(XMM2);
710 if (o >= GOF(XMM3) && o+sz <= GOF(XMM3)+SZB(XMM3)) return GOF(XMM3);
711 if (o >= GOF(XMM4) && o+sz <= GOF(XMM4)+SZB(XMM4)) return GOF(XMM4);
712 if (o >= GOF(XMM5) && o+sz <= GOF(XMM5)+SZB(XMM5)) return GOF(XMM5);
713 if (o >= GOF(XMM6) && o+sz <= GOF(XMM6)+SZB(XMM6)) return GOF(XMM6);
714 if (o >= GOF(XMM7) && o+sz <= GOF(XMM7)+SZB(XMM7)) return GOF(XMM7);
715
716 /* MMX accesses to FP regs. Need to allow for 32-bit references
717 due to dirty helpers for frstor etc, which reference the entire
718 64-byte block in one go. */
719 if (o >= GOF(FPREG[0])
720 && o+sz <= GOF(FPREG[0])+SZB(FPREG[0])) return GOF(FPREG[0]);
721 if (o >= GOF(FPREG[1])
722 && o+sz <= GOF(FPREG[1])+SZB(FPREG[1])) return GOF(FPREG[1]);
723 if (o >= GOF(FPREG[2])
724 && o+sz <= GOF(FPREG[2])+SZB(FPREG[2])) return GOF(FPREG[2]);
725 if (o >= GOF(FPREG[3])
726 && o+sz <= GOF(FPREG[3])+SZB(FPREG[3])) return GOF(FPREG[3]);
727 if (o >= GOF(FPREG[4])
728 && o+sz <= GOF(FPREG[4])+SZB(FPREG[4])) return GOF(FPREG[4]);
729 if (o >= GOF(FPREG[5])
730 && o+sz <= GOF(FPREG[5])+SZB(FPREG[5])) return GOF(FPREG[5]);
731 if (o >= GOF(FPREG[6])
732 && o+sz <= GOF(FPREG[6])+SZB(FPREG[6])) return GOF(FPREG[6]);
733 if (o >= GOF(FPREG[7])
734 && o+sz <= GOF(FPREG[7])+SZB(FPREG[7])) return GOF(FPREG[7]);
735
736 /* skip %GS and other segment related stuff. We could shadow
737 guest_LDT and guest_GDT, although it seems pointless.
738 guest_CS .. guest_SS are too small to shadow directly and it
739 also seems pointless to shadow them indirectly (that is, in
740 the style of %AH .. %DH). */
741 if (o == GOF(CS) && sz == 2) return -1;
742 if (o == GOF(DS) && sz == 2) return -1;
743 if (o == GOF(ES) && sz == 2) return -1;
744 if (o == GOF(FS) && sz == 2) return -1;
745 if (o == GOF(GS) && sz == 2) return -1;
746 if (o == GOF(SS) && sz == 2) return -1;
747 if (o == GOF(LDT) && sz == 4) return -1;
748 if (o == GOF(GDT) && sz == 4) return -1;
749
750 VG_(printf)("MC_(get_otrack_shadow_offset)(x86)(off=%d,sz=%d)\n",
751 offset,szB);
752 tl_assert(0);
753# undef GOF
754# undef SZB
755
sewardjb5b87402011-03-07 16:05:35 +0000[diff] [blame]756 /* -------------------- s390x -------------------- */
757
758# elif defined(VGA_s390x)
759# define GOF(_fieldname) \
760 (offsetof(VexGuestS390XState,guest_##_fieldname))
761 Int o = offset;
762 Int sz = szB;
763 tl_assert(sz > 0);
764 tl_assert(host_is_big_endian());
765
766 /* no matter what byte(s) we change, we have changed the full 8 byte value
767 and need to track this change for the whole register */
768 if (o >= GOF(r0) && sz <= 8 && o <= (GOF(r15) + 8 - sz))
769 return GOF(r0) + ((o-GOF(r0)) & -8) ;
770
771
772 /* fprs are accessed 4 or 8 byte at once. Again, we track that change for
773 the full register */
774 if ((sz == 8 || sz == 4) && o >= GOF(f0) && o <= GOF(f15)+8-sz)
775 return GOF(f0) + ((o-GOF(f0)) & -8) ;
776
777 /* access registers are accessed 4 bytes at once */
778 if (sz == 4 && o >= GOF(a0) && o <= GOF(a15))
florian30e2d652012-09-03 17:34:22 +0000[diff] [blame]779 return o;
sewardjb5b87402011-03-07 16:05:35 +0000[diff] [blame]780
781 /* we access the guest counter either fully or one of the 4byte words */
782 if (o == GOF(counter) && (sz == 8 || sz ==4))
783 return o;
784 if (o == GOF(counter) + 4 && sz == 4)
785 return o;
786
florian30e2d652012-09-03 17:34:22 +0000[diff] [blame]787 if (o == GOF(EMNOTE) && sz == 4) return -1;
788
789 if (o == GOF(CC_OP) && sz == 8) return -1;
florian234955d2013-05-31 15:44:06 +0000[diff] [blame]790 /* We access CC_DEP1 either fully or bits [0:31] */
791 if (o == GOF(CC_DEP1) && (sz == 8 || sz ==4))
792 return o;
florian30e2d652012-09-03 17:34:22 +0000[diff] [blame]793 if (o == GOF(CC_DEP2) && sz == 8) return o;
794 if (o == GOF(CC_NDEP) && sz == 8) return -1;
sewardj1146ae62014-05-04 10:54:08 +0000[diff] [blame]795 if (o == GOF(CMSTART) && sz == 8) return -1;
796 if (o == GOF(CMLEN) && sz == 8) return -1;
florian30e2d652012-09-03 17:34:22 +0000[diff] [blame]797 if (o == GOF(NRADDR) && sz == 8) return -1;
798 if (o == GOF(IP_AT_SYSCALL) && sz == 8) return -1;
florian4fea8402012-09-11 23:06:02 +0000[diff] [blame]799 if (o == GOF(fpc) && sz == 4) return -1;
florian30e2d652012-09-03 17:34:22 +0000[diff] [blame]800 if (o == GOF(IA) && sz == 8) return -1;
801 if (o == (GOF(IA) + 4) && sz == 4) return -1;
802 if (o == GOF(SYSNO) && sz == 8) return -1;
sewardjb5b87402011-03-07 16:05:35 +0000[diff] [blame]803 VG_(printf)("MC_(get_otrack_shadow_offset)(s390x)(off=%d,sz=%d)\n",
804 offset,szB);
805 tl_assert(0);
806# undef GOF
807
808
sewardj59570ff2010-01-01 11:59:33 +0000[diff] [blame]809 /* --------------------- arm --------------------- */
810
811# elif defined(VGA_arm)
812
813# define GOF(_fieldname) \
814 (offsetof(VexGuestARMState,guest_##_fieldname))
815# define SZB(_fieldname) \
816 (sizeof(((VexGuestARMState*)0)->guest_##_fieldname))
817
818 Int o = offset;
819 Int sz = szB;
820 tl_assert(sz > 0);
821 tl_assert(host_is_little_endian());
822
823 if (o == GOF(R0) && sz == 4) return o;
824 if (o == GOF(R1) && sz == 4) return o;
825 if (o == GOF(R2) && sz == 4) return o;
826 if (o == GOF(R3) && sz == 4) return o;
827 if (o == GOF(R4) && sz == 4) return o;
828 if (o == GOF(R5) && sz == 4) return o;
829 if (o == GOF(R6) && sz == 4) return o;
830 if (o == GOF(R7) && sz == 4) return o;
831 if (o == GOF(R8) && sz == 4) return o;
832 if (o == GOF(R9) && sz == 4) return o;
833 if (o == GOF(R10) && sz == 4) return o;
834 if (o == GOF(R11) && sz == 4) return o;
835 if (o == GOF(R12) && sz == 4) return o;
836 if (o == GOF(R13) && sz == 4) return o;
837 if (o == GOF(R14) && sz == 4) return o;
838
839 /* EAZG: These may be completely wrong. */
sewardjca9054a2010-08-22 12:16:25 +0000[diff] [blame]840 if (o == GOF(R15T) && sz == 4) return -1; /* slot unused */
sewardj59570ff2010-01-01 11:59:33 +0000[diff] [blame]841 if (o == GOF(CC_OP) && sz == 4) return -1; /* slot unused */
842
843 if (o == GOF(CC_DEP1) && sz == 4) return o;
844 if (o == GOF(CC_DEP2) && sz == 4) return o;
845
846 if (o == GOF(CC_NDEP) && sz == 4) return -1; /* slot unused */
847
sewardjca9054a2010-08-22 12:16:25 +0000[diff] [blame]848 if (o == GOF(QFLAG32) && sz == 4) return o;
849
sewardj6fede422010-09-22 22:27:41 +0000[diff] [blame]850 if (o == GOF(GEFLAG0) && sz == 4) return o;
851 if (o == GOF(GEFLAG1) && sz == 4) return o;
852 if (o == GOF(GEFLAG2) && sz == 4) return o;
853 if (o == GOF(GEFLAG3) && sz == 4) return o;
854
sewardj59570ff2010-01-01 11:59:33 +0000[diff] [blame]855 //if (o == GOF(SYSCALLNO) && sz == 4) return -1; /* slot unused */
856 //if (o == GOF(CC) && sz == 4) return -1; /* slot unused */
florian2e497412012-08-26 03:22:09 +0000[diff] [blame]857 //if (o == GOF(EMNOTE) && sz == 4) return -1; /* slot unused */
sewardj1146ae62014-05-04 10:54:08 +0000[diff] [blame]858 //if (o == GOF(CMSTART) && sz == 4) return -1; /* slot unused */
sewardj59570ff2010-01-01 11:59:33 +0000[diff] [blame]859 //if (o == GOF(NRADDR) && sz == 4) return -1; /* slot unused */
860
861 if (o == GOF(FPSCR) && sz == 4) return -1;
862 if (o == GOF(TPIDRURO) && sz == 4) return -1;
sewardjca9054a2010-08-22 12:16:25 +0000[diff] [blame]863 if (o == GOF(ITSTATE) && sz == 4) return -1;
sewardj59570ff2010-01-01 11:59:33 +0000[diff] [blame]864
sewardj8f6ec702010-09-29 21:40:44 +0000[diff] [blame]865 /* Accesses to F or D registers */
866 if (sz == 4 || sz == 8) {
867 if (o >= GOF(D0) && o+sz <= GOF(D0) +SZB(D0)) return GOF(D0);
868 if (o >= GOF(D1) && o+sz <= GOF(D1) +SZB(D1)) return GOF(D1);
869 if (o >= GOF(D2) && o+sz <= GOF(D2) +SZB(D2)) return GOF(D2);
870 if (o >= GOF(D3) && o+sz <= GOF(D3) +SZB(D3)) return GOF(D3);
871 if (o >= GOF(D4) && o+sz <= GOF(D4) +SZB(D4)) return GOF(D4);
872 if (o >= GOF(D5) && o+sz <= GOF(D5) +SZB(D5)) return GOF(D5);
873 if (o >= GOF(D6) && o+sz <= GOF(D6) +SZB(D6)) return GOF(D6);
874 if (o >= GOF(D7) && o+sz <= GOF(D7) +SZB(D7)) return GOF(D7);
875 if (o >= GOF(D8) && o+sz <= GOF(D8) +SZB(D8)) return GOF(D8);
876 if (o >= GOF(D9) && o+sz <= GOF(D9) +SZB(D9)) return GOF(D9);
877 if (o >= GOF(D10) && o+sz <= GOF(D10)+SZB(D10)) return GOF(D10);
878 if (o >= GOF(D11) && o+sz <= GOF(D11)+SZB(D11)) return GOF(D11);
879 if (o >= GOF(D12) && o+sz <= GOF(D12)+SZB(D12)) return GOF(D12);
880 if (o >= GOF(D13) && o+sz <= GOF(D13)+SZB(D13)) return GOF(D13);
881 if (o >= GOF(D14) && o+sz <= GOF(D14)+SZB(D14)) return GOF(D14);
882 if (o >= GOF(D15) && o+sz <= GOF(D15)+SZB(D15)) return GOF(D15);
883 if (o >= GOF(D16) && o+sz <= GOF(D16)+SZB(D16)) return GOF(D16);
884 if (o >= GOF(D17) && o+sz <= GOF(D17)+SZB(D17)) return GOF(D17);
885 if (o >= GOF(D18) && o+sz <= GOF(D18)+SZB(D18)) return GOF(D18);
886 if (o >= GOF(D19) && o+sz <= GOF(D19)+SZB(D19)) return GOF(D19);
887 if (o >= GOF(D20) && o+sz <= GOF(D20)+SZB(D20)) return GOF(D20);
888 if (o >= GOF(D21) && o+sz <= GOF(D21)+SZB(D21)) return GOF(D21);
889 if (o >= GOF(D22) && o+sz <= GOF(D22)+SZB(D22)) return GOF(D22);
890 if (o >= GOF(D23) && o+sz <= GOF(D23)+SZB(D23)) return GOF(D23);
891 if (o >= GOF(D24) && o+sz <= GOF(D24)+SZB(D24)) return GOF(D24);
892 if (o >= GOF(D25) && o+sz <= GOF(D25)+SZB(D25)) return GOF(D25);
893 if (o >= GOF(D26) && o+sz <= GOF(D26)+SZB(D26)) return GOF(D26);
894 if (o >= GOF(D27) && o+sz <= GOF(D27)+SZB(D27)) return GOF(D27);
895 if (o >= GOF(D28) && o+sz <= GOF(D28)+SZB(D28)) return GOF(D28);
896 if (o >= GOF(D29) && o+sz <= GOF(D29)+SZB(D29)) return GOF(D29);
897 if (o >= GOF(D30) && o+sz <= GOF(D30)+SZB(D30)) return GOF(D30);
898 if (o >= GOF(D31) && o+sz <= GOF(D31)+SZB(D31)) return GOF(D31);
899 }
900
901 /* Accesses to Q registers */
902 if (sz == 16) {
903 if (o >= GOF(D0) && o+sz <= GOF(D0) +2*SZB(D0)) return GOF(D0); // Q0
904 if (o >= GOF(D2) && o+sz <= GOF(D2) +2*SZB(D2)) return GOF(D2); // Q1
905 if (o >= GOF(D4) && o+sz <= GOF(D4) +2*SZB(D4)) return GOF(D4); // Q2
906 if (o >= GOF(D6) && o+sz <= GOF(D6) +2*SZB(D6)) return GOF(D6); // Q3
907 if (o >= GOF(D8) && o+sz <= GOF(D8) +2*SZB(D8)) return GOF(D8); // Q4
908 if (o >= GOF(D10) && o+sz <= GOF(D10)+2*SZB(D10)) return GOF(D10); // Q5
909 if (o >= GOF(D12) && o+sz <= GOF(D12)+2*SZB(D12)) return GOF(D12); // Q6
910 if (o >= GOF(D14) && o+sz <= GOF(D14)+2*SZB(D14)) return GOF(D14); // Q7
911 if (o >= GOF(D16) && o+sz <= GOF(D16)+2*SZB(D16)) return GOF(D16); // Q8
912 if (o >= GOF(D18) && o+sz <= GOF(D18)+2*SZB(D18)) return GOF(D18); // Q9
913 if (o >= GOF(D20) && o+sz <= GOF(D20)+2*SZB(D20)) return GOF(D20); // Q10
914 if (o >= GOF(D22) && o+sz <= GOF(D22)+2*SZB(D22)) return GOF(D22); // Q11
915 if (o >= GOF(D24) && o+sz <= GOF(D24)+2*SZB(D24)) return GOF(D24); // Q12
916 if (o >= GOF(D26) && o+sz <= GOF(D26)+2*SZB(D26)) return GOF(D26); // Q13
917 if (o >= GOF(D28) && o+sz <= GOF(D28)+2*SZB(D28)) return GOF(D28); // Q14
918 if (o >= GOF(D30) && o+sz <= GOF(D30)+2*SZB(D30)) return GOF(D30); // Q15
919 }
sewardj59570ff2010-01-01 11:59:33 +0000[diff] [blame]920
sewardj1146ae62014-05-04 10:54:08 +0000[diff] [blame]921 if (o == GOF(CMSTART) && sz == 4) return -1;
922 if (o == GOF(CMLEN) && sz == 4) return -1;
sewardjb29b6492012-12-13 15:17:40 +0000[diff] [blame]923
sewardj59570ff2010-01-01 11:59:33 +0000[diff] [blame]924 VG_(printf)("MC_(get_otrack_shadow_offset)(arm)(off=%d,sz=%d)\n",
925 offset,szB);
926 tl_assert(0);
927# undef GOF
928# undef SZB
929
sewardjf0c12502014-01-12 12:54:00 +0000[diff] [blame]930 /* --------------------- arm64 --------------------- */
931
932# elif defined(VGA_arm64)
933
934# define GOF(_fieldname) \
935 (offsetof(VexGuestARM64State,guest_##_fieldname))
936# define SZB(_fieldname) \
937 (sizeof(((VexGuestARM64State*)0)->guest_##_fieldname))
938
sewardjda7e0462014-02-27 11:15:58 +0000[diff] [blame]939 Int o = offset;
940 Int sz = szB;
941 Bool is48 = sz == 8 || sz == 4;
942
sewardjf0c12502014-01-12 12:54:00 +0000[diff] [blame]943 tl_assert(sz > 0);
944 tl_assert(host_is_little_endian());
sewardjda7e0462014-02-27 11:15:58 +0000[diff] [blame]945
946 if (o == GOF(X0) && is48) return o;
947 if (o == GOF(X1) && is48) return o;
948 if (o == GOF(X2) && is48) return o;
949 if (o == GOF(X3) && is48) return o;
sewardj85d45142014-04-08 15:26:12 +0000[diff] [blame]950 if (o == GOF(X4) && is48) return o;
951 if (o == GOF(X5) && is48) return o;
952 if (o == GOF(X6) && is48) return o;
953 if (o == GOF(X7) && is48) return o;
954 if (o == GOF(X8) && is48) return o;
955 if (o == GOF(X9) && is48) return o;
956 if (o == GOF(X10) && is48) return o;
957 if (o == GOF(X11) && is48) return o;
958 if (o == GOF(X12) && is48) return o;
959 if (o == GOF(X13) && is48) return o;
960 if (o == GOF(X14) && is48) return o;
961 if (o == GOF(X15) && is48) return o;
962 if (o == GOF(X16) && is48) return o;
963 if (o == GOF(X17) && is48) return o;
964 if (o == GOF(X18) && is48) return o;
965 if (o == GOF(X19) && is48) return o;
966 if (o == GOF(X20) && is48) return o;
967 if (o == GOF(X21) && is48) return o;
968 if (o == GOF(X22) && is48) return o;
969 if (o == GOF(X23) && is48) return o;
970 if (o == GOF(X24) && is48) return o;
971 if (o == GOF(X25) && is48) return o;
972 if (o == GOF(X26) && is48) return o;
973 if (o == GOF(X27) && is48) return o;
974 if (o == GOF(X28) && is48) return o;
975 if (o == GOF(X29) && is48) return o;
976 if (o == GOF(X30) && is48) return o;
977 if (o == GOF(XSP) && is48) return o;
978
979 if (o == GOF(PC) && is48) return -1; // untracked
980 if (o == GOF(CC_DEP1) && sz == 8) return o;
981 if (o == GOF(CC_DEP2) && sz == 8) return o;
982
983 if (o == GOF(CC_OP) && sz == 8) return -1; // untracked
984 if (o == GOF(CC_NDEP) && sz == 8) return -1; // untracked
985 if (o == GOF(TPIDR_EL0) && sz == 8) return -1; // untracked
986
987 if (o >= GOF(Q0) && o+sz <= GOF(Q0) +SZB(Q0)) return GOF(Q0);
988 if (o >= GOF(Q1) && o+sz <= GOF(Q1) +SZB(Q1)) return GOF(Q1);
989 if (o >= GOF(Q2) && o+sz <= GOF(Q2) +SZB(Q2)) return GOF(Q2);
990 if (o >= GOF(Q3) && o+sz <= GOF(Q3) +SZB(Q3)) return GOF(Q3);
991 if (o >= GOF(Q4) && o+sz <= GOF(Q4) +SZB(Q4)) return GOF(Q4);
992 if (o >= GOF(Q5) && o+sz <= GOF(Q5) +SZB(Q5)) return GOF(Q5);
993 if (o >= GOF(Q6) && o+sz <= GOF(Q6) +SZB(Q6)) return GOF(Q6);
994 if (o >= GOF(Q7) && o+sz <= GOF(Q7) +SZB(Q7)) return GOF(Q7);
995 if (o >= GOF(Q8) && o+sz <= GOF(Q8) +SZB(Q8)) return GOF(Q8);
996 if (o >= GOF(Q9) && o+sz <= GOF(Q9) +SZB(Q9)) return GOF(Q9);
997 if (o >= GOF(Q10) && o+sz <= GOF(Q10)+SZB(Q10)) return GOF(Q10);
998 if (o >= GOF(Q11) && o+sz <= GOF(Q11)+SZB(Q11)) return GOF(Q11);
999 if (o >= GOF(Q12) && o+sz <= GOF(Q12)+SZB(Q12)) return GOF(Q12);
1000 if (o >= GOF(Q13) && o+sz <= GOF(Q13)+SZB(Q13)) return GOF(Q13);
1001 if (o >= GOF(Q14) && o+sz <= GOF(Q14)+SZB(Q14)) return GOF(Q14);
1002 if (o >= GOF(Q15) && o+sz <= GOF(Q15)+SZB(Q15)) return GOF(Q15);
1003 if (o >= GOF(Q16) && o+sz <= GOF(Q16)+SZB(Q16)) return GOF(Q16);
1004 if (o >= GOF(Q17) && o+sz <= GOF(Q17)+SZB(Q17)) return GOF(Q17);
1005 if (o >= GOF(Q18) && o+sz <= GOF(Q18)+SZB(Q18)) return GOF(Q18);
1006 if (o >= GOF(Q19) && o+sz <= GOF(Q19)+SZB(Q19)) return GOF(Q19);
1007 if (o >= GOF(Q20) && o+sz <= GOF(Q20)+SZB(Q20)) return GOF(Q20);
1008 if (o >= GOF(Q21) && o+sz <= GOF(Q21)+SZB(Q21)) return GOF(Q21);
1009 if (o >= GOF(Q22) && o+sz <= GOF(Q22)+SZB(Q22)) return GOF(Q22);
1010 if (o >= GOF(Q23) && o+sz <= GOF(Q23)+SZB(Q23)) return GOF(Q23);
1011 if (o >= GOF(Q24) && o+sz <= GOF(Q24)+SZB(Q24)) return GOF(Q24);
1012 if (o >= GOF(Q25) && o+sz <= GOF(Q25)+SZB(Q25)) return GOF(Q25);
1013 if (o >= GOF(Q26) && o+sz <= GOF(Q26)+SZB(Q26)) return GOF(Q26);
1014 if (o >= GOF(Q27) && o+sz <= GOF(Q27)+SZB(Q27)) return GOF(Q27);
1015 if (o >= GOF(Q28) && o+sz <= GOF(Q28)+SZB(Q28)) return GOF(Q28);
1016 if (o >= GOF(Q29) && o+sz <= GOF(Q29)+SZB(Q29)) return GOF(Q29);
1017 if (o >= GOF(Q30) && o+sz <= GOF(Q30)+SZB(Q30)) return GOF(Q30);
1018 if (o >= GOF(Q31) && o+sz <= GOF(Q31)+SZB(Q31)) return GOF(Q31);
1019
1020 if (o == GOF(FPCR) && sz == 4) return -1; // untracked
sewardjc69477a2014-06-28 22:12:34 +0000[diff] [blame]1021 if (o == GOF(QCFLAG) && sz == 16) return o;
sewardjf0c12502014-01-12 12:54:00 +0000[diff] [blame]1022
sewardj1146ae62014-05-04 10:54:08 +0000[diff] [blame]1023 if (o == GOF(CMSTART) && sz == 8) return -1; // untracked
1024 if (o == GOF(CMLEN) && sz == 8) return -1; // untracked
sewardjc76d0e52014-05-03 21:22:55 +0000[diff] [blame]1025
sewardjf0c12502014-01-12 12:54:00 +0000[diff] [blame]1026 VG_(printf)("MC_(get_otrack_shadow_offset)(arm64)(off=%d,sz=%d)\n",
1027 offset,szB);
1028 tl_assert(0);
1029# undef GOF
1030# undef SZB
1031
sewardj5db15402012-06-07 09:13:21 +0000[diff] [blame]1032 /* --------------------- mips32 --------------------- */
1033
1034# elif defined(VGA_mips32)
1035
1036# define GOF(_fieldname) \
1037 (offsetof(VexGuestMIPS32State,guest_##_fieldname))
1038# define SZB(_fieldname) \
1039 (sizeof(((VexGuestMIPS32State*)0)->guest_##_fieldname))
1040
1041 Int o = offset;
1042 Int sz = szB;
1043 tl_assert(sz > 0);
1044# if defined (VG_LITTLEENDIAN)
1045 tl_assert(host_is_little_endian());
1046# elif defined (VG_BIGENDIAN)
1047 tl_assert(host_is_big_endian());
1048# else
1049# error "Unknown endianness"
1050# endif
1051
1052 if (o == GOF(r0) && sz == 4) return o;
1053 if (o == GOF(r1) && sz == 4) return o;
1054 if (o == GOF(r2) && sz == 4) return o;
1055 if (o == GOF(r3) && sz == 4) return o;
1056 if (o == GOF(r4) && sz == 4) return o;
1057 if (o == GOF(r5) && sz == 4) return o;
1058 if (o == GOF(r6) && sz == 4) return o;
1059 if (o == GOF(r7) && sz == 4) return o;
1060 if (o == GOF(r8) && sz == 4) return o;
1061 if (o == GOF(r9) && sz == 4) return o;
1062 if (o == GOF(r10) && sz == 4) return o;
1063 if (o == GOF(r11) && sz == 4) return o;
1064 if (o == GOF(r12) && sz == 4) return o;
1065 if (o == GOF(r13) && sz == 4) return o;
1066 if (o == GOF(r14) && sz == 4) return o;
1067 if (o == GOF(r15) && sz == 4) return o;
1068 if (o == GOF(r16) && sz == 4) return o;
1069 if (o == GOF(r17) && sz == 4) return o;
1070 if (o == GOF(r18) && sz == 4) return o;
1071 if (o == GOF(r19) && sz == 4) return o;
1072 if (o == GOF(r20) && sz == 4) return o;
1073 if (o == GOF(r21) && sz == 4) return o;
1074 if (o == GOF(r22) && sz == 4) return o;
1075 if (o == GOF(r23) && sz == 4) return o;
1076 if (o == GOF(r24) && sz == 4) return o;
1077 if (o == GOF(r25) && sz == 4) return o;
1078 if (o == GOF(r26) && sz == 4) return o;
1079 if (o == GOF(r27) && sz == 4) return o;
1080 if (o == GOF(r28) && sz == 4) return o;
1081 if (o == GOF(r29) && sz == 4) return o;
1082 if (o == GOF(r30) && sz == 4) return o;
1083 if (o == GOF(r31) && sz == 4) return o;
1084 if (o == GOF(PC) && sz == 4) return -1; /* slot unused */
1085
1086 if (o == GOF(HI) && sz == 4) return o;
1087 if (o == GOF(LO) && sz == 4) return o;
1088
1089 if (o == GOF(FIR) && sz == 4) return -1; /* slot unused */
1090 if (o == GOF(FCCR) && sz == 4) return -1; /* slot unused */
1091 if (o == GOF(FEXR) && sz == 4) return -1; /* slot unused */
1092 if (o == GOF(FENR) && sz == 4) return -1; /* slot unused */
1093 if (o == GOF(FCSR) && sz == 4) return -1; /* slot unused */
1094 if (o == GOF(ULR) && sz == 4) return -1;
1095
florian2e497412012-08-26 03:22:09 +0000[diff] [blame]1096 if (o == GOF(EMNOTE) && sz == 4) return -1; /* slot unused */
sewardj1146ae62014-05-04 10:54:08 +0000[diff] [blame]1097 if (o == GOF(CMSTART) && sz == 4) return -1; /* slot unused */
1098 if (o == GOF(CMLEN) && sz == 4) return -1; /* slot unused */
sewardj5db15402012-06-07 09:13:21 +0000[diff] [blame]1099 if (o == GOF(NRADDR) && sz == 4) return -1; /* slot unused */
1100
1101 if (o >= GOF(f0) && o+sz <= GOF(f0) +SZB(f0)) return GOF(f0);
1102 if (o >= GOF(f1) && o+sz <= GOF(f1) +SZB(f1)) return GOF(f1);
1103 if (o >= GOF(f2) && o+sz <= GOF(f2) +SZB(f2)) return GOF(f2);
1104 if (o >= GOF(f3) && o+sz <= GOF(f3) +SZB(f3)) return GOF(f3);
1105 if (o >= GOF(f4) && o+sz <= GOF(f4) +SZB(f4)) return GOF(f4);
1106 if (o >= GOF(f5) && o+sz <= GOF(f5) +SZB(f5)) return GOF(f5);
1107 if (o >= GOF(f6) && o+sz <= GOF(f6) +SZB(f6)) return GOF(f6);
1108 if (o >= GOF(f7) && o+sz <= GOF(f7) +SZB(f7)) return GOF(f7);
1109 if (o >= GOF(f8) && o+sz <= GOF(f8) +SZB(f8)) return GOF(f8);
1110 if (o >= GOF(f9) && o+sz <= GOF(f9) +SZB(f9)) return GOF(f9);
1111 if (o >= GOF(f10) && o+sz <= GOF(f10)+SZB(f10)) return GOF(f10);
1112 if (o >= GOF(f11) && o+sz <= GOF(f11)+SZB(f11)) return GOF(f11);
1113 if (o >= GOF(f12) && o+sz <= GOF(f12)+SZB(f12)) return GOF(f12);
1114 if (o >= GOF(f13) && o+sz <= GOF(f13)+SZB(f13)) return GOF(f13);
1115 if (o >= GOF(f14) && o+sz <= GOF(f14)+SZB(f14)) return GOF(f14);
1116 if (o >= GOF(f15) && o+sz <= GOF(f15)+SZB(f15)) return GOF(f15);
1117
1118 if (o >= GOF(f16) && o+sz <= GOF(f16)+SZB(f16)) return GOF(f16);
1119 if (o >= GOF(f17) && o+sz <= GOF(f17) +SZB(f17)) return GOF(f17);
1120 if (o >= GOF(f18) && o+sz <= GOF(f18) +SZB(f18)) return GOF(f18);
1121 if (o >= GOF(f19) && o+sz <= GOF(f19) +SZB(f19)) return GOF(f19);
1122 if (o >= GOF(f20) && o+sz <= GOF(f20) +SZB(f20)) return GOF(f20);
1123 if (o >= GOF(f21) && o+sz <= GOF(f21) +SZB(f21)) return GOF(f21);
1124 if (o >= GOF(f22) && o+sz <= GOF(f22) +SZB(f22)) return GOF(f22);
1125 if (o >= GOF(f23) && o+sz <= GOF(f23) +SZB(f23)) return GOF(f23);
1126 if (o >= GOF(f24) && o+sz <= GOF(f24) +SZB(f24)) return GOF(f24);
1127 if (o >= GOF(f25) && o+sz <= GOF(f25) +SZB(f25)) return GOF(f25);
1128 if (o >= GOF(f26) && o+sz <= GOF(f26)+SZB(f26)) return GOF(f26);
1129 if (o >= GOF(f27) && o+sz <= GOF(f27)+SZB(f27)) return GOF(f27);
1130 if (o >= GOF(f28) && o+sz <= GOF(f28)+SZB(f28)) return GOF(f28);
1131 if (o >= GOF(f29) && o+sz <= GOF(f29)+SZB(f29)) return GOF(f29);
1132 if (o >= GOF(f30) && o+sz <= GOF(f30)+SZB(f30)) return GOF(f30);
1133 if (o >= GOF(f31) && o+sz <= GOF(f31)+SZB(f31)) return GOF(f31);
1134
dejanj5f790e82013-07-25 08:22:08 +0000[diff] [blame]1135 /* Slot unused. */
1136 if ((o > GOF(NRADDR)) && (o <= GOF(NRADDR) +12 )) return -1;
1137
1138 /* MIPS32 DSP ASE(r2) specific registers. */
1139 if (o == GOF(DSPControl) && sz == 4) return o;
1140 if (o == GOF(ac0) && sz == 8) return o;
1141 if (o == GOF(ac1) && sz == 8) return o;
1142 if (o == GOF(ac2) && sz == 8) return o;
1143 if (o == GOF(ac3) && sz == 8) return o;
sewardj5db15402012-06-07 09:13:21 +0000[diff] [blame]1144
1145 VG_(printf)("MC_(get_otrack_shadow_offset)(mips)(off=%d,sz=%d)\n",
1146 offset,szB);
1147 tl_assert(0);
1148# undef GOF
1149# undef SZB
1150
petarj4df0bfc2013-02-27 23:17:33 +0000[diff] [blame]1151 /* --------------------- mips64 --------------------- */
1152
1153# elif defined(VGA_mips64)
1154
1155# define GOF(_fieldname) \
1156 (offsetof(VexGuestMIPS64State,guest_##_fieldname))
1157# define SZB(_fieldname) \
1158 (sizeof(((VexGuestMIPS64State*)0)->guest_##_fieldname))
1159
1160 Int o = offset;
1161 Int sz = szB;
1162 tl_assert(sz > 0);
1163#if defined (VG_LITTLEENDIAN)
1164 tl_assert(host_is_little_endian());
1165#elif defined (VG_BIGENDIAN)
1166 tl_assert(host_is_big_endian());
1167#endif
1168
1169 if (o >= GOF(r0) && sz <= 8 && o <= (GOF(r31) + 8 - sz))
1170 return GOF(r0) + ((o-GOF(r0)) & -8) ;
1171
1172 if (o == GOF(PC) && sz == 8) return -1; /* slot unused */
1173
1174 if (o == GOF(HI) && sz == 8) return o;
1175 if (o == GOF(LO) && sz == 8) return o;
1176
1177 if (o == GOF(FIR) && sz == 4) return -1; /* slot unused */
1178 if (o == GOF(FCCR) && sz == 4) return -1; /* slot unused */
1179 if (o == GOF(FEXR) && sz == 4) return -1; /* slot unused */
1180 if (o == GOF(FENR) && sz == 4) return -1; /* slot unused */
1181 if (o == GOF(FCSR) && sz == 4) return -1; /* slot unused */
1182 if (o == GOF(ULR) && sz == 8) return o;
1183
1184 if (o == GOF(EMNOTE) && sz == 4) return -1; /* slot unused */
sewardj1146ae62014-05-04 10:54:08 +0000[diff] [blame]1185 if (o == GOF(CMSTART) && sz == 4) return -1; /* slot unused */
1186 if (o == GOF(CMLEN) && sz == 4) return -1; /* slot unused */
petarj4df0bfc2013-02-27 23:17:33 +0000[diff] [blame]1187 if (o == GOF(NRADDR) && sz == 4) return -1; /* slot unused */
1188
1189 if (o >= GOF(f0) && o+sz <= GOF(f0) +SZB(f0)) return GOF(f0);
1190 if (o >= GOF(f1) && o+sz <= GOF(f1) +SZB(f1)) return GOF(f1);
1191 if (o >= GOF(f2) && o+sz <= GOF(f2) +SZB(f2)) return GOF(f2);
1192 if (o >= GOF(f3) && o+sz <= GOF(f3) +SZB(f3)) return GOF(f3);
1193 if (o >= GOF(f4) && o+sz <= GOF(f4) +SZB(f4)) return GOF(f4);
1194 if (o >= GOF(f5) && o+sz <= GOF(f5) +SZB(f5)) return GOF(f5);
1195 if (o >= GOF(f6) && o+sz <= GOF(f6) +SZB(f6)) return GOF(f6);
1196 if (o >= GOF(f7) && o+sz <= GOF(f7) +SZB(f7)) return GOF(f7);
1197 if (o >= GOF(f8) && o+sz <= GOF(f8) +SZB(f8)) return GOF(f8);
1198 if (o >= GOF(f9) && o+sz <= GOF(f9) +SZB(f9)) return GOF(f9);
1199 if (o >= GOF(f10) && o+sz <= GOF(f10)+SZB(f10)) return GOF(f10);
1200 if (o >= GOF(f11) && o+sz <= GOF(f11)+SZB(f11)) return GOF(f11);
1201 if (o >= GOF(f12) && o+sz <= GOF(f12)+SZB(f12)) return GOF(f12);
1202 if (o >= GOF(f13) && o+sz <= GOF(f13)+SZB(f13)) return GOF(f13);
1203 if (o >= GOF(f14) && o+sz <= GOF(f14)+SZB(f14)) return GOF(f14);
1204 if (o >= GOF(f15) && o+sz <= GOF(f15)+SZB(f15)) return GOF(f15);
1205 if (o >= GOF(f16) && o+sz <= GOF(f16)+SZB(f16)) return GOF(f16);
1206 if (o >= GOF(f17) && o+sz <= GOF(f17)+SZB(f17)) return GOF(f17);
1207 if (o >= GOF(f18) && o+sz <= GOF(f18)+SZB(f18)) return GOF(f18);
1208 if (o >= GOF(f19) && o+sz <= GOF(f19)+SZB(f19)) return GOF(f19);
1209 if (o >= GOF(f20) && o+sz <= GOF(f20)+SZB(f20)) return GOF(f20);
1210 if (o >= GOF(f21) && o+sz <= GOF(f21)+SZB(f21)) return GOF(f21);
1211 if (o >= GOF(f22) && o+sz <= GOF(f22)+SZB(f22)) return GOF(f22);
1212 if (o >= GOF(f23) && o+sz <= GOF(f23)+SZB(f23)) return GOF(f23);
1213 if (o >= GOF(f24) && o+sz <= GOF(f24)+SZB(f24)) return GOF(f24);
1214 if (o >= GOF(f25) && o+sz <= GOF(f25)+SZB(f25)) return GOF(f25);
1215 if (o >= GOF(f26) && o+sz <= GOF(f26)+SZB(f26)) return GOF(f26);
1216 if (o >= GOF(f27) && o+sz <= GOF(f27)+SZB(f27)) return GOF(f27);
1217 if (o >= GOF(f28) && o+sz <= GOF(f28)+SZB(f28)) return GOF(f28);
1218 if (o >= GOF(f29) && o+sz <= GOF(f29)+SZB(f29)) return GOF(f29);
1219 if (o >= GOF(f30) && o+sz <= GOF(f30)+SZB(f30)) return GOF(f30);
1220 if (o >= GOF(f31) && o+sz <= GOF(f31)+SZB(f31)) return GOF(f31);
1221
1222 if ((o > GOF(NRADDR)) && (o <= GOF(NRADDR) +12 )) return -1;
1223
1224 VG_(printf)("MC_(get_otrack_shadow_offset)(mips)(off=%d,sz=%d)\n",
1225 offset,szB);
1226 tl_assert(0);
1227# undef GOF
1228# undef SZB
1229
sewardj7cf4e6b2008-05-01 20:24:26 +0000[diff] [blame]1230# else
1231# error "FIXME: not implemented for this architecture"
1232# endif
1233}
1234
1235
1236/* Let 'arr' describe an indexed reference to a guest state section
1237 (guest state array).
1238
1239 This function returns the corresponding guest state type to be used
1240 when indexing the corresponding array in the second shadow (origin
1241 tracking) area. If the array is not to be origin-tracked, return
1242 Ity_INVALID.
1243
1244 This function must agree with MC_(get_otrack_shadow_offset) above.
1245 See comments at the start of MC_(get_otrack_shadow_offset).
1246*/
1247IRType MC_(get_otrack_reg_array_equiv_int_type) ( IRRegArray* arr )
1248{
1249 /* -------------------- ppc64 -------------------- */
carllcae0cc22014-08-07 23:17:29 +0000[diff] [blame]1250# if defined(VGA_ppc64be) || defined(VGA_ppc64le)
sewardj7cf4e6b2008-05-01 20:24:26 +0000[diff] [blame]1251 /* The redir stack. */
1252 if (arr->base == offsetof(VexGuestPPC64State,guest_REDIR_STACK[0])
1253 && arr->elemTy == Ity_I64
1254 && arr->nElems == VEX_GUEST_PPC64_REDIR_STACK_SIZE)
1255 return Ity_I64;
1256
1257 VG_(printf)("get_reg_array_equiv_int_type(ppc64): unhandled: ");
1258 ppIRRegArray(arr);
1259 VG_(printf)("\n");
1260 tl_assert(0);
1261
1262 /* -------------------- ppc32 -------------------- */
1263# elif defined(VGA_ppc32)
1264 /* The redir stack. */
1265 if (arr->base == offsetof(VexGuestPPC32State,guest_REDIR_STACK[0])
1266 && arr->elemTy == Ity_I32
1267 && arr->nElems == VEX_GUEST_PPC32_REDIR_STACK_SIZE)
1268 return Ity_I32;
1269
1270 VG_(printf)("get_reg_array_equiv_int_type(ppc32): unhandled: ");
1271 ppIRRegArray(arr);
1272 VG_(printf)("\n");
1273 tl_assert(0);
1274
1275 /* -------------------- amd64 -------------------- */
1276# elif defined(VGA_amd64)
1277 /* Ignore the FP tag array - pointless to shadow, and in any case
1278 the elements are too small */
1279 if (arr->base == offsetof(VexGuestAMD64State,guest_FPTAG)
1280 && arr->elemTy == Ity_I8 && arr->nElems == 8)
1281 return Ity_INVALID;
1282
1283 /* The FP register array */
1284 if (arr->base == offsetof(VexGuestAMD64State,guest_FPREG[0])
1285 && arr->elemTy == Ity_F64 && arr->nElems == 8)
1286 return Ity_I64;
1287
1288 VG_(printf)("get_reg_array_equiv_int_type(amd64): unhandled: ");
1289 ppIRRegArray(arr);
1290 VG_(printf)("\n");
1291 tl_assert(0);
1292
1293 /* --------------------- x86 --------------------- */
1294# elif defined(VGA_x86)
1295 /* Ignore the FP tag array - pointless to shadow, and in any case
1296 the elements are too small */
1297 if (arr->base == offsetof(VexGuestX86State,guest_FPTAG)
1298 && arr->elemTy == Ity_I8 && arr->nElems == 8)
1299 return Ity_INVALID;
1300
1301 /* The FP register array */
1302 if (arr->base == offsetof(VexGuestX86State,guest_FPREG[0])
1303 && arr->elemTy == Ity_F64 && arr->nElems == 8)
1304 return Ity_I64;
1305
1306 VG_(printf)("get_reg_array_equiv_int_type(x86): unhandled: ");
1307 ppIRRegArray(arr);
1308 VG_(printf)("\n");
1309 tl_assert(0);
1310
sewardj59570ff2010-01-01 11:59:33 +0000[diff] [blame]1311 /* --------------------- arm --------------------- */
1312# elif defined(VGA_arm)
sewardj59570ff2010-01-01 11:59:33 +0000[diff] [blame]1313 VG_(printf)("get_reg_array_equiv_int_type(arm): unhandled: ");
1314 ppIRRegArray(arr);
1315 VG_(printf)("\n");
1316 tl_assert(0);
1317
sewardjf0c12502014-01-12 12:54:00 +0000[diff] [blame]1318 /* --------------------- arm64 --------------------- */
1319# elif defined(VGA_arm64)
1320 VG_(printf)("get_reg_array_equiv_int_type(arm64): unhandled: ");
1321 ppIRRegArray(arr);
1322 VG_(printf)("\n");
1323 tl_assert(0);
1324
sewardjb5b87402011-03-07 16:05:35 +0000[diff] [blame]1325 /* --------------------- s390x --------------------- */
1326# elif defined(VGA_s390x)
1327 /* Should never het here because s390x does not use Ist_PutI
1328 and Iex_GetI. */
1329 tl_assert(0);
sewardj5db15402012-06-07 09:13:21 +0000[diff] [blame]1330
1331/* --------------------- mips32 --------------------- */
1332# elif defined(VGA_mips32)
1333 VG_(printf)("get_reg_array_equiv_int_type(mips32): unhandled: ");
1334 ppIRRegArray(arr);
1335 VG_(printf)("\n");
1336 tl_assert(0);
1337
petarj4df0bfc2013-02-27 23:17:33 +0000[diff] [blame]1338 /* --------------------- mips64 --------------------- */
1339# elif defined(VGA_mips64)
1340 VG_(printf)("get_reg_array_equiv_int_type(mips64): unhandled: ");
1341 ppIRRegArray(arr);
1342 VG_(printf)("\n");
1343 tl_assert(0);
sewardj7cf4e6b2008-05-01 20:24:26 +0000[diff] [blame]1344# else
1345# error "FIXME: not implemented for this architecture"
1346# endif
1347}
1348
1349
1350/*--------------------------------------------------------------------*/
1351/*--- end mc_machine.c ---*/
1352/*--------------------------------------------------------------------*/