sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 1 | |
| 2 | /*---------------------------------------------------------------*/ |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 3 | /*--- begin guest_arm_defs.h ---*/ |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 4 | /*---------------------------------------------------------------*/ |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 5 | /* |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 6 | This file is part of Valgrind, a dynamic binary instrumentation |
| 7 | framework. |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 8 | |
sewardj | 89ae847 | 2013-10-18 14:12:58 +0000 | [diff] [blame] | 9 | Copyright (C) 2004-2013 OpenWorks LLP |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 10 | info@open-works.net |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 11 | |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 12 | This program is free software; you can redistribute it and/or |
| 13 | modify it under the terms of the GNU General Public License as |
| 14 | published by the Free Software Foundation; either version 2 of the |
| 15 | License, or (at your option) any later version. |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 16 | |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 17 | This program is distributed in the hope that it will be useful, but |
| 18 | WITHOUT ANY WARRANTY; without even the implied warranty of |
| 19 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 20 | General Public License for more details. |
| 21 | |
| 22 | You should have received a copy of the GNU General Public License |
| 23 | along with this program; if not, write to the Free Software |
| 24 | Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA |
sewardj | 7bd6ffe | 2005-08-03 16:07:36 +0000 | [diff] [blame] | 25 | 02110-1301, USA. |
| 26 | |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 27 | The GNU General Public License is contained in the file COPYING. |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 28 | */ |
| 29 | |
| 30 | /* Only to be used within the guest-arm directory. */ |
| 31 | |
sewardj | cef7d3e | 2009-07-02 12:21:59 +0000 | [diff] [blame] | 32 | #ifndef __VEX_GUEST_ARM_DEFS_H |
| 33 | #define __VEX_GUEST_ARM_DEFS_H |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 34 | |
florian | 58a637b | 2012-09-30 20:30:17 +0000 | [diff] [blame] | 35 | #include "libvex_basictypes.h" |
| 36 | #include "guest_generic_bb_to_IR.h" // DisResult |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 37 | |
| 38 | /*---------------------------------------------------------*/ |
| 39 | /*--- arm to IR conversion ---*/ |
| 40 | /*---------------------------------------------------------*/ |
| 41 | |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 42 | /* Convert one ARM insn to IR. See the type DisOneInstrFn in |
| 43 | bb_to_IR.h. */ |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 44 | extern |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 45 | DisResult disInstr_ARM ( IRSB* irbb, |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 46 | Bool (*resteerOkFn) ( void*, Addr64 ), |
sewardj | 984d9b1 | 2010-01-15 10:53:21 +0000 | [diff] [blame] | 47 | Bool resteerCisOk, |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 48 | void* callback_opaque, |
| 49 | UChar* guest_code, |
| 50 | Long delta, |
| 51 | Addr64 guest_IP, |
| 52 | VexArch guest_arch, |
| 53 | VexArchInfo* archinfo, |
| 54 | VexAbiInfo* abiinfo, |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame^] | 55 | VexEndness host_endness, |
sewardj | 442e51a | 2012-12-06 18:08:04 +0000 | [diff] [blame] | 56 | Bool sigill_diag ); |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 57 | |
| 58 | /* Used by the optimiser to specialise calls to helpers. */ |
| 59 | extern |
florian | 1ff4756 | 2012-10-21 02:09:51 +0000 | [diff] [blame] | 60 | IRExpr* guest_arm_spechelper ( const HChar* function_name, |
sewardj | d266447 | 2010-08-22 12:44:20 +0000 | [diff] [blame] | 61 | IRExpr** args, |
| 62 | IRStmt** precedingStmts, |
| 63 | Int n_precedingStmts ); |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 64 | |
| 65 | /* Describes to the optimser which part of the guest state require |
| 66 | precise memory exceptions. This is logically part of the guest |
| 67 | state description. */ |
| 68 | extern |
| 69 | Bool guest_arm_state_requires_precise_mem_exns ( Int, Int ); |
| 70 | |
| 71 | extern |
| 72 | VexGuestLayout armGuest_layout; |
| 73 | |
| 74 | |
| 75 | /*---------------------------------------------------------*/ |
| 76 | /*--- arm guest helpers ---*/ |
| 77 | /*---------------------------------------------------------*/ |
| 78 | |
| 79 | /* --- CLEAN HELPERS --- */ |
| 80 | |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 81 | /* Calculate NZCV from the supplied thunk components, in the positions |
| 82 | they appear in the CPSR, viz bits 31:28 for N Z V C respectively. |
| 83 | Returned bits 27:0 are zero. */ |
| 84 | extern |
| 85 | UInt armg_calculate_flags_nzcv ( UInt cc_op, UInt cc_dep1, |
| 86 | UInt cc_dep2, UInt cc_dep3 ); |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 87 | |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 88 | /* Calculate the C flag from the thunk components, in the lowest bit |
| 89 | of the word (bit 0). */ |
| 90 | extern |
| 91 | UInt armg_calculate_flag_c ( UInt cc_op, UInt cc_dep1, |
| 92 | UInt cc_dep2, UInt cc_dep3 ); |
| 93 | |
| 94 | /* Calculate the V flag from the thunk components, in the lowest bit |
| 95 | of the word (bit 0). */ |
| 96 | extern |
| 97 | UInt armg_calculate_flag_v ( UInt cc_op, UInt cc_dep1, |
| 98 | UInt cc_dep2, UInt cc_dep3 ); |
| 99 | |
| 100 | /* Calculate the specified condition from the thunk components, in the |
| 101 | lowest bit of the word (bit 0). */ |
| 102 | extern |
| 103 | UInt armg_calculate_condition ( UInt cond_n_op /* ARMCondcode << 4 | cc_op */, |
| 104 | UInt cc_dep1, |
| 105 | UInt cc_dep2, UInt cc_dep3 ); |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 106 | |
sewardj | d266447 | 2010-08-22 12:44:20 +0000 | [diff] [blame] | 107 | /* Calculate the QC flag from the thunk components, in the lowest bit |
| 108 | of the word (bit 0). */ |
| 109 | extern |
| 110 | UInt armg_calculate_flag_qc ( UInt resL1, UInt resL2, |
| 111 | UInt resR1, UInt resR2 ); |
| 112 | |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 113 | |
| 114 | /*---------------------------------------------------------*/ |
| 115 | /*--- Condition code stuff ---*/ |
| 116 | /*---------------------------------------------------------*/ |
| 117 | |
| 118 | /* Flags masks. Defines positions of flags bits in the CPSR. */ |
| 119 | #define ARMG_CC_SHIFT_N 31 |
| 120 | #define ARMG_CC_SHIFT_Z 30 |
| 121 | #define ARMG_CC_SHIFT_C 29 |
| 122 | #define ARMG_CC_SHIFT_V 28 |
sewardj | d266447 | 2010-08-22 12:44:20 +0000 | [diff] [blame] | 123 | #define ARMG_CC_SHIFT_Q 27 |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 124 | |
| 125 | #define ARMG_CC_MASK_N (1 << ARMG_CC_SHIFT_N) |
| 126 | #define ARMG_CC_MASK_Z (1 << ARMG_CC_SHIFT_Z) |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 127 | #define ARMG_CC_MASK_C (1 << ARMG_CC_SHIFT_C) |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 128 | #define ARMG_CC_MASK_V (1 << ARMG_CC_SHIFT_V) |
sewardj | d266447 | 2010-08-22 12:44:20 +0000 | [diff] [blame] | 129 | #define ARMG_CC_MASK_Q (1 << ARMG_CC_SHIFT_Q) |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 130 | |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 131 | /* Flag thunk descriptors. A four-word thunk is used to record |
sewardj | d266447 | 2010-08-22 12:44:20 +0000 | [diff] [blame] | 132 | details of the most recent flag-setting operation, so NZCV can |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 133 | be computed later if needed. |
| 134 | |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 135 | The four words are: |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 136 | |
| 137 | CC_OP, which describes the operation. |
| 138 | |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 139 | CC_DEP1, CC_DEP2, CC_DEP3. These are arguments to the |
| 140 | operation. We want set up the mcx_masks in flag helper calls |
| 141 | involving these fields so that Memcheck "believes" that the |
| 142 | resulting flags are data-dependent on both CC_DEP1 and |
| 143 | CC_DEP2. Hence the name DEP. |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 144 | |
| 145 | When building the thunk, it is always necessary to write words into |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 146 | CC_DEP1/2/3, even if those args are not used given the |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 147 | CC_OP field. This is important because otherwise Memcheck could |
| 148 | give false positives as it does not understand the relationship |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 149 | between the CC_OP field and CC_DEP1/2/3, and so believes |
| 150 | that the definedness of the stored flags always depends on |
| 151 | all 3 DEP values. |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 152 | |
sewardj | bb8b394 | 2011-05-01 18:47:10 +0000 | [diff] [blame] | 153 | Fields carrying only 1 or 2 bits of useful information (old_C, |
| 154 | shifter_co, old_V, oldC:oldV) must have their top 31 or 30 bits |
| 155 | (respectively) zero. The text "31x0:" or "30x0:" denotes this. |
| 156 | |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 157 | A summary of the field usages is: |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 158 | |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 159 | OP DEP1 DEP2 DEP3 |
| 160 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 161 | |
sewardj | da9a9f5 | 2012-04-20 22:32:34 +0000 | [diff] [blame] | 162 | OP_COPY curr_NZCV:28x0 unused unused |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 163 | OP_ADD argL argR unused |
| 164 | OP_SUB argL argR unused |
sewardj | bb8b394 | 2011-05-01 18:47:10 +0000 | [diff] [blame] | 165 | OP_ADC argL argR 31x0:old_C |
| 166 | OP_SBB argL argR 31x0:old_C |
| 167 | OP_LOGIC result 31x0:shifter_co 31x0:old_V |
| 168 | OP_MUL result unused 30x0:old_C:old_V |
| 169 | OP_MULL resLO32 resHI32 30x0:old_C:old_V |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 170 | */ |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 171 | |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 172 | enum { |
| 173 | ARMG_CC_OP_COPY=0, /* DEP1 = NZCV in 31:28, DEP2 = 0, DEP3 = 0 |
| 174 | just copy DEP1 to output */ |
| 175 | |
| 176 | ARMG_CC_OP_ADD, /* DEP1 = argL (Rn), DEP2 = argR (shifter_op), |
| 177 | DEP3 = 0 */ |
| 178 | |
| 179 | ARMG_CC_OP_SUB, /* DEP1 = argL (Rn), DEP2 = argR (shifter_op), |
| 180 | DEP3 = 0 */ |
| 181 | |
| 182 | ARMG_CC_OP_ADC, /* DEP1 = argL (Rn), DEP2 = arg2 (shifter_op), |
| 183 | DEP3 = oldC (in LSB) */ |
| 184 | |
| 185 | ARMG_CC_OP_SBB, /* DEP1 = argL (Rn), DEP2 = arg2 (shifter_op), |
| 186 | DEP3 = oldC (in LSB) */ |
| 187 | |
| 188 | ARMG_CC_OP_LOGIC, /* DEP1 = result, DEP2 = shifter_carry_out (in LSB), |
| 189 | DEP3 = old V flag (in LSB) */ |
| 190 | |
| 191 | ARMG_CC_OP_MUL, /* DEP1 = result, DEP2 = 0, DEP3 = oldC:old_V |
| 192 | (in bits 1:0) */ |
| 193 | |
| 194 | ARMG_CC_OP_MULL, /* DEP1 = resLO32, DEP2 = resHI32, DEP3 = oldC:old_V |
| 195 | (in bits 1:0) */ |
| 196 | |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 197 | ARMG_CC_OP_NUMBER |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 198 | }; |
| 199 | |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 200 | /* XXXX because of the calling conventions for |
| 201 | armg_calculate_condition, all this OP values MUST be in the range |
| 202 | 0 .. 15 only (viz, 4-bits). */ |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 203 | |
| 204 | |
| 205 | |
| 206 | /* Defines conditions which we can ask for (ARM ARM 2e page A3-6) */ |
| 207 | |
| 208 | typedef |
| 209 | enum { |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 210 | ARMCondEQ = 0, /* equal : Z=1 */ |
| 211 | ARMCondNE = 1, /* not equal : Z=0 */ |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 212 | |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 213 | ARMCondHS = 2, /* >=u (higher or same) : C=1 */ |
| 214 | ARMCondLO = 3, /* <u (lower) : C=0 */ |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 215 | |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 216 | ARMCondMI = 4, /* minus (negative) : N=1 */ |
| 217 | ARMCondPL = 5, /* plus (zero or +ve) : N=0 */ |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 218 | |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 219 | ARMCondVS = 6, /* overflow : V=1 */ |
| 220 | ARMCondVC = 7, /* no overflow : V=0 */ |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 221 | |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 222 | ARMCondHI = 8, /* >u (higher) : C=1 && Z=0 */ |
| 223 | ARMCondLS = 9, /* <=u (lower or same) : C=0 || Z=1 */ |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 224 | |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 225 | ARMCondGE = 10, /* >=s (signed greater or equal) : N=V */ |
| 226 | ARMCondLT = 11, /* <s (signed less than) : N!=V */ |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 227 | |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 228 | ARMCondGT = 12, /* >s (signed greater) : Z=0 && N=V */ |
| 229 | ARMCondLE = 13, /* <=s (signed less or equal) : Z=1 || N!=V */ |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 230 | |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 231 | ARMCondAL = 14, /* always (unconditional) : 1 */ |
| 232 | ARMCondNV = 15 /* never (unconditional): : 0 */ |
| 233 | /* NB: ARM have deprecated the use of the NV condition code. |
| 234 | You are now supposed to use MOV R0,R0 as a noop rather than |
| 235 | MOVNV R0,R0 as was previously recommended. Future processors |
| 236 | may have the NV condition code reused to do other things. */ |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 237 | } |
| 238 | ARMCondcode; |
| 239 | |
sewardj | cef7d3e | 2009-07-02 12:21:59 +0000 | [diff] [blame] | 240 | #endif /* ndef __VEX_GUEST_ARM_DEFS_H */ |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 241 | |
| 242 | /*---------------------------------------------------------------*/ |
sewardj | cef7d3e | 2009-07-02 12:21:59 +0000 | [diff] [blame] | 243 | /*--- end guest_arm_defs.h ---*/ |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 244 | /*---------------------------------------------------------------*/ |