sewardj | ec6ad59 | 2004-06-20 12:26:53 +0000 | [diff] [blame] | 1 | |
| 2 | /*---------------------------------------------------------------*/ |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 3 | /*--- begin libvex_ir.h ---*/ |
sewardj | ec6ad59 | 2004-06-20 12:26:53 +0000 | [diff] [blame] | 4 | /*---------------------------------------------------------------*/ |
| 5 | |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 6 | /* |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 7 | This file is part of Valgrind, a dynamic binary instrumentation |
| 8 | framework. |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 9 | |
sewardj | 25e5473 | 2012-08-05 15:36:51 +0000 | [diff] [blame] | 10 | Copyright (C) 2004-2012 OpenWorks LLP |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 11 | info@open-works.net |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 12 | |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 13 | This program is free software; you can redistribute it and/or |
| 14 | modify it under the terms of the GNU General Public License as |
| 15 | published by the Free Software Foundation; either version 2 of the |
| 16 | License, or (at your option) any later version. |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 17 | |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 18 | This program is distributed in the hope that it will be useful, but |
| 19 | WITHOUT ANY WARRANTY; without even the implied warranty of |
| 20 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 21 | General Public License for more details. |
| 22 | |
| 23 | You should have received a copy of the GNU General Public License |
| 24 | along with this program; if not, write to the Free Software |
| 25 | Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA |
sewardj | 7bd6ffe | 2005-08-03 16:07:36 +0000 | [diff] [blame] | 26 | 02110-1301, USA. |
| 27 | |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 28 | The GNU General Public License is contained in the file COPYING. |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 29 | |
| 30 | Neither the names of the U.S. Department of Energy nor the |
| 31 | University of California nor the names of its contributors may be |
| 32 | used to endorse or promote products derived from this software |
| 33 | without prior written permission. |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 34 | */ |
| 35 | |
sewardj | 887a11a | 2004-07-05 17:26:47 +0000 | [diff] [blame] | 36 | #ifndef __LIBVEX_IR_H |
| 37 | #define __LIBVEX_IR_H |
sewardj | ac9af02 | 2004-07-05 01:15:34 +0000 | [diff] [blame] | 38 | |
sewardj | 887a11a | 2004-07-05 17:26:47 +0000 | [diff] [blame] | 39 | #include "libvex_basictypes.h" |
sewardj | ec6ad59 | 2004-06-20 12:26:53 +0000 | [diff] [blame] | 40 | |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 41 | |
sewardj | ec6ad59 | 2004-06-20 12:26:53 +0000 | [diff] [blame] | 42 | /*---------------------------------------------------------------*/ |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 43 | /*--- High-level IR description ---*/ |
| 44 | /*---------------------------------------------------------------*/ |
| 45 | |
| 46 | /* Vex IR is an architecture-neutral intermediate representation. |
| 47 | Unlike some IRs in systems similar to Vex, it is not like assembly |
| 48 | language (ie. a list of instructions). Rather, it is more like the |
| 49 | IR that might be used in a compiler. |
| 50 | |
| 51 | Code blocks |
| 52 | ~~~~~~~~~~~ |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 53 | The code is broken into small code blocks ("superblocks", type: |
| 54 | 'IRSB'). Each code block typically represents from 1 to perhaps 50 |
| 55 | instructions. IRSBs are single-entry, multiple-exit code blocks. |
| 56 | Each IRSB contains three things: |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 57 | - a type environment, which indicates the type of each temporary |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 58 | value present in the IRSB |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 59 | - a list of statements, which represent code |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 60 | - a jump that exits from the end the IRSB |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 61 | Because the blocks are multiple-exit, there can be additional |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 62 | conditional exit statements that cause control to leave the IRSB |
| 63 | before the final exit. Also because of this, IRSBs can cover |
| 64 | multiple non-consecutive sequences of code (up to 3). These are |
| 65 | recorded in the type VexGuestExtents (see libvex.h). |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 66 | |
| 67 | Statements and expressions |
| 68 | ~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 69 | Statements (type 'IRStmt') represent operations with side-effects, |
| 70 | eg. guest register writes, stores, and assignments to temporaries. |
| 71 | Expressions (type 'IRExpr') represent operations without |
| 72 | side-effects, eg. arithmetic operations, loads, constants. |
| 73 | Expressions can contain sub-expressions, forming expression trees, |
| 74 | eg. (3 + (4 * load(addr1)). |
| 75 | |
| 76 | Storage of guest state |
| 77 | ~~~~~~~~~~~~~~~~~~~~~~ |
| 78 | The "guest state" contains the guest registers of the guest machine |
| 79 | (ie. the machine that we are simulating). It is stored by default |
| 80 | in a block of memory supplied by the user of the VEX library, |
| 81 | generally referred to as the guest state (area). To operate on |
| 82 | these registers, one must first read ("Get") them from the guest |
| 83 | state into a temporary value. Afterwards, one can write ("Put") |
| 84 | them back into the guest state. |
| 85 | |
| 86 | Get and Put are characterised by a byte offset into the guest |
| 87 | state, a small integer which effectively gives the identity of the |
| 88 | referenced guest register, and a type, which indicates the size of |
| 89 | the value to be transferred. |
| 90 | |
| 91 | The basic "Get" and "Put" operations are sufficient to model normal |
| 92 | fixed registers on the guest. Selected areas of the guest state |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 93 | can be treated as a circular array of registers (type: |
| 94 | 'IRRegArray'), which can be indexed at run-time. This is done with |
| 95 | the "GetI" and "PutI" primitives. This is necessary to describe |
| 96 | rotating register files, for example the x87 FPU stack, SPARC |
| 97 | register windows, and the Itanium register files. |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 98 | |
| 99 | Examples, and flattened vs. unflattened code |
| 100 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 101 | For example, consider this x86 instruction: |
| 102 | |
| 103 | addl %eax, %ebx |
| 104 | |
| 105 | One Vex IR translation for this code would be this: |
| 106 | |
sewardj | 2f10aa6 | 2011-05-27 13:20:56 +0000 | [diff] [blame] | 107 | ------ IMark(0x24F275, 7, 0) ------ |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 108 | t3 = GET:I32(0) # get %eax, a 32-bit integer |
| 109 | t2 = GET:I32(12) # get %ebx, a 32-bit integer |
| 110 | t1 = Add32(t3,t2) # addl |
| 111 | PUT(0) = t1 # put %eax |
| 112 | |
| 113 | (For simplicity, this ignores the effects on the condition codes, and |
| 114 | the update of the instruction pointer.) |
| 115 | |
| 116 | The "IMark" is an IR statement that doesn't represent actual code. |
| 117 | Instead it indicates the address and length of the original |
| 118 | instruction. The numbers 0 and 12 are offsets into the guest state |
| 119 | for %eax and %ebx. The full list of offsets for an architecture |
| 120 | <ARCH> can be found in the type VexGuest<ARCH>State in the file |
| 121 | VEX/pub/libvex_guest_<ARCH>.h. |
| 122 | |
| 123 | The five statements in this example are: |
| 124 | - the IMark |
| 125 | - three assignments to temporaries |
| 126 | - one register write (put) |
| 127 | |
| 128 | The six expressions in this example are: |
| 129 | - two register reads (gets) |
| 130 | - one arithmetic (add) operation |
| 131 | - three temporaries (two nested within the Add32, one in the PUT) |
| 132 | |
| 133 | The above IR is "flattened", ie. all sub-expressions are "atoms", |
| 134 | either constants or temporaries. An equivalent, unflattened version |
| 135 | would be: |
| 136 | |
| 137 | PUT(0) = Add32(GET:I32(0), GET:I32(12)) |
| 138 | |
| 139 | IR is guaranteed to be flattened at instrumentation-time. This makes |
| 140 | instrumentation easier. Equivalent flattened and unflattened IR |
| 141 | typically results in the same generated code. |
| 142 | |
| 143 | Another example, this one showing loads and stores: |
| 144 | |
| 145 | addl %edx,4(%eax) |
| 146 | |
| 147 | This becomes (again ignoring condition code and instruction pointer |
| 148 | updates): |
| 149 | |
sewardj | 2f10aa6 | 2011-05-27 13:20:56 +0000 | [diff] [blame] | 150 | ------ IMark(0x4000ABA, 3, 0) ------ |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 151 | t3 = Add32(GET:I32(0),0x4:I32) |
| 152 | t2 = LDle:I32(t3) |
| 153 | t1 = GET:I32(8) |
| 154 | t0 = Add32(t2,t1) |
| 155 | STle(t3) = t0 |
| 156 | |
| 157 | The "le" in "LDle" and "STle" is short for "little-endian". |
| 158 | |
| 159 | No need for deallocations |
| 160 | ~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 161 | Although there are allocation functions for various data structures |
| 162 | in this file, there are no deallocation functions. This is because |
| 163 | Vex uses a memory allocation scheme that automatically reclaims the |
| 164 | memory used by allocated structures once translation is completed. |
| 165 | This makes things easier for tools that instruments/transforms code |
| 166 | blocks. |
| 167 | |
| 168 | SSAness and typing |
| 169 | ~~~~~~~~~~~~~~~~~~ |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 170 | The IR is fully typed. For every IRSB (IR block) it is possible to |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 171 | say unambiguously whether or not it is correctly typed. |
| 172 | Incorrectly typed IR has no meaning and the VEX will refuse to |
| 173 | process it. At various points during processing VEX typechecks the |
| 174 | IR and aborts if any violations are found. This seems overkill but |
| 175 | makes it a great deal easier to build a reliable JIT. |
| 176 | |
| 177 | IR also has the SSA property. SSA stands for Static Single |
| 178 | Assignment, and what it means is that each IR temporary may be |
| 179 | assigned to only once. This idea became widely used in compiler |
| 180 | construction in the mid to late 90s. It makes many IR-level |
| 181 | transformations/code improvements easier, simpler and faster. |
| 182 | Whenever it typechecks an IR block, VEX also checks the SSA |
| 183 | property holds, and will abort if not so. So SSAness is |
| 184 | mechanically and rigidly enforced. |
| 185 | */ |
| 186 | |
| 187 | /*---------------------------------------------------------------*/ |
sewardj | ac6b712 | 2004-06-27 01:03:57 +0000 | [diff] [blame] | 188 | /*--- Type definitions for the IR ---*/ |
sewardj | ec6ad59 | 2004-06-20 12:26:53 +0000 | [diff] [blame] | 189 | /*---------------------------------------------------------------*/ |
| 190 | |
sewardj | 496a58d | 2005-03-20 18:44:44 +0000 | [diff] [blame] | 191 | /* General comments about naming schemes: |
| 192 | |
| 193 | All publically visible functions contain the name of the primary |
| 194 | type on which they operate (IRFoo, IRBar, etc). Hence you should |
| 195 | be able to identify these functions by grepping for "IR[A-Z]". |
| 196 | |
| 197 | For some type 'IRFoo': |
| 198 | |
| 199 | - ppIRFoo is the printing method for IRFoo, printing it to the |
| 200 | output channel specified in the LibVEX_Initialise call. |
| 201 | |
| 202 | - eqIRFoo is a structural equality predicate for IRFoos. |
| 203 | |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 204 | - deepCopyIRFoo is a deep copy constructor for IRFoos. |
sewardj | 496a58d | 2005-03-20 18:44:44 +0000 | [diff] [blame] | 205 | It recursively traverses the entire argument tree and |
sewardj | f6c8ebf | 2007-02-06 01:52:52 +0000 | [diff] [blame] | 206 | produces a complete new tree. All types have a deep copy |
| 207 | constructor. |
sewardj | 496a58d | 2005-03-20 18:44:44 +0000 | [diff] [blame] | 208 | |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 209 | - shallowCopyIRFoo is the shallow copy constructor for IRFoos. |
sewardj | 496a58d | 2005-03-20 18:44:44 +0000 | [diff] [blame] | 210 | It creates a new top-level copy of the supplied object, |
sewardj | f6c8ebf | 2007-02-06 01:52:52 +0000 | [diff] [blame] | 211 | but does not copy any sub-objects. Only some types have a |
| 212 | shallow copy constructor. |
sewardj | 496a58d | 2005-03-20 18:44:44 +0000 | [diff] [blame] | 213 | */ |
| 214 | |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 215 | /* ------------------ Types ------------------ */ |
sewardj | e3d0d2e | 2004-06-27 10:42:44 +0000 | [diff] [blame] | 216 | |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 217 | /* A type indicates the size of a value, and whether it's an integer, a |
| 218 | float, or a vector (SIMD) value. */ |
sewardj | e3d0d2e | 2004-06-27 10:42:44 +0000 | [diff] [blame] | 219 | typedef |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 220 | enum { |
sewardj | cfe046e | 2013-01-17 14:23:53 +0000 | [diff] [blame] | 221 | Ity_INVALID=0x1100, |
sewardj | c4356f0 | 2007-11-09 21:15:04 +0000 | [diff] [blame] | 222 | Ity_I1, |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 223 | Ity_I8, |
| 224 | Ity_I16, |
| 225 | Ity_I32, |
| 226 | Ity_I64, |
sewardj | 9b96767 | 2005-02-08 11:13:09 +0000 | [diff] [blame] | 227 | Ity_I128, /* 128-bit scalar */ |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 228 | Ity_F32, /* IEEE 754 float */ |
| 229 | Ity_F64, /* IEEE 754 double */ |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 230 | Ity_D32, /* 32-bit Decimal floating point */ |
| 231 | Ity_D64, /* 64-bit Decimal floating point */ |
| 232 | Ity_D128, /* 128-bit Decimal floating point */ |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 233 | Ity_F128, /* 128-bit floating point; implementation defined */ |
sewardj | c4530ae | 2012-05-21 10:18:49 +0000 | [diff] [blame] | 234 | Ity_V128, /* 128-bit SIMD */ |
| 235 | Ity_V256 /* 256-bit SIMD */ |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 236 | } |
sewardj | e3d0d2e | 2004-06-27 10:42:44 +0000 | [diff] [blame] | 237 | IRType; |
| 238 | |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 239 | /* Pretty-print an IRType */ |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 240 | extern void ppIRType ( IRType ); |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 241 | |
| 242 | /* Get the size (in bytes) of an IRType */ |
| 243 | extern Int sizeofIRType ( IRType ); |
sewardj | e3d0d2e | 2004-06-27 10:42:44 +0000 | [diff] [blame] | 244 | |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 245 | |
sewardj | af1ceca | 2005-06-30 23:31:27 +0000 | [diff] [blame] | 246 | /* ------------------ Endianness ------------------ */ |
| 247 | |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 248 | /* IREndness is used in load IRExprs and store IRStmts. */ |
sewardj | af1ceca | 2005-06-30 23:31:27 +0000 | [diff] [blame] | 249 | typedef |
| 250 | enum { |
sewardj | cfe046e | 2013-01-17 14:23:53 +0000 | [diff] [blame] | 251 | Iend_LE=0x1200, /* little endian */ |
sewardj | c4356f0 | 2007-11-09 21:15:04 +0000 | [diff] [blame] | 252 | Iend_BE /* big endian */ |
sewardj | af1ceca | 2005-06-30 23:31:27 +0000 | [diff] [blame] | 253 | } |
| 254 | IREndness; |
| 255 | |
| 256 | |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 257 | /* ------------------ Constants ------------------ */ |
sewardj | ec6ad59 | 2004-06-20 12:26:53 +0000 | [diff] [blame] | 258 | |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 259 | /* IRConsts are used within 'Const' and 'Exit' IRExprs. */ |
| 260 | |
| 261 | /* The various kinds of constant. */ |
sewardj | ac6b712 | 2004-06-27 01:03:57 +0000 | [diff] [blame] | 262 | typedef |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 263 | enum { |
sewardj | cfe046e | 2013-01-17 14:23:53 +0000 | [diff] [blame] | 264 | Ico_U1=0x1300, |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 265 | Ico_U8, |
| 266 | Ico_U16, |
| 267 | Ico_U32, |
| 268 | Ico_U64, |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 269 | Ico_F32, /* 32-bit IEEE754 floating */ |
| 270 | Ico_F32i, /* 32-bit unsigned int to be interpreted literally |
| 271 | as a IEEE754 single value. */ |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 272 | Ico_F64, /* 64-bit IEEE754 floating */ |
| 273 | Ico_F64i, /* 64-bit unsigned int to be interpreted literally |
| 274 | as a IEEE754 double value. */ |
sewardj | 37a505b | 2012-06-29 15:28:24 +0000 | [diff] [blame] | 275 | Ico_V128, /* 128-bit restricted vector constant, with 1 bit |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 276 | (repeated 8 times) for each of the 16 x 1-byte lanes */ |
sewardj | 37a505b | 2012-06-29 15:28:24 +0000 | [diff] [blame] | 277 | Ico_V256 /* 256-bit restricted vector constant, with 1 bit |
| 278 | (repeated 8 times) for each of the 32 x 1-byte lanes */ |
sewardj | 207557a | 2004-08-27 12:00:18 +0000 | [diff] [blame] | 279 | } |
sewardj | ac6b712 | 2004-06-27 01:03:57 +0000 | [diff] [blame] | 280 | IRConstTag; |
| 281 | |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 282 | /* A constant. Stored as a tagged union. 'tag' indicates what kind of |
| 283 | constant this is. 'Ico' is the union that holds the fields. If an |
| 284 | IRConst 'c' has c.tag equal to Ico_U32, then it's a 32-bit constant, |
| 285 | and its value can be accessed with 'c.Ico.U32'. */ |
sewardj | ac6b712 | 2004-06-27 01:03:57 +0000 | [diff] [blame] | 286 | typedef |
sewardj | e3d0d2e | 2004-06-27 10:42:44 +0000 | [diff] [blame] | 287 | struct _IRConst { |
sewardj | ac6b712 | 2004-06-27 01:03:57 +0000 | [diff] [blame] | 288 | IRConstTag tag; |
| 289 | union { |
sewardj | ba99931 | 2004-11-15 15:21:17 +0000 | [diff] [blame] | 290 | Bool U1; |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 291 | UChar U8; |
| 292 | UShort U16; |
| 293 | UInt U32; |
| 294 | ULong U64; |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 295 | Float F32; |
| 296 | UInt F32i; |
sewardj | a58ea66 | 2004-08-15 03:12:41 +0000 | [diff] [blame] | 297 | Double F64; |
sewardj | 17442fe | 2004-09-20 14:54:28 +0000 | [diff] [blame] | 298 | ULong F64i; |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 299 | UShort V128; /* 16-bit value; see Ico_V128 comment above */ |
sewardj | 37a505b | 2012-06-29 15:28:24 +0000 | [diff] [blame] | 300 | UInt V256; /* 32-bit value; see Ico_V256 comment above */ |
sewardj | ac6b712 | 2004-06-27 01:03:57 +0000 | [diff] [blame] | 301 | } Ico; |
| 302 | } |
| 303 | IRConst; |
sewardj | ec6ad59 | 2004-06-20 12:26:53 +0000 | [diff] [blame] | 304 | |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 305 | /* IRConst constructors */ |
sewardj | ba99931 | 2004-11-15 15:21:17 +0000 | [diff] [blame] | 306 | extern IRConst* IRConst_U1 ( Bool ); |
sewardj | 17442fe | 2004-09-20 14:54:28 +0000 | [diff] [blame] | 307 | extern IRConst* IRConst_U8 ( UChar ); |
| 308 | extern IRConst* IRConst_U16 ( UShort ); |
| 309 | extern IRConst* IRConst_U32 ( UInt ); |
| 310 | extern IRConst* IRConst_U64 ( ULong ); |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 311 | extern IRConst* IRConst_F32 ( Float ); |
| 312 | extern IRConst* IRConst_F32i ( UInt ); |
sewardj | 17442fe | 2004-09-20 14:54:28 +0000 | [diff] [blame] | 313 | extern IRConst* IRConst_F64 ( Double ); |
| 314 | extern IRConst* IRConst_F64i ( ULong ); |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 315 | extern IRConst* IRConst_V128 ( UShort ); |
sewardj | 37a505b | 2012-06-29 15:28:24 +0000 | [diff] [blame] | 316 | extern IRConst* IRConst_V256 ( UInt ); |
sewardj | ec6ad59 | 2004-06-20 12:26:53 +0000 | [diff] [blame] | 317 | |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 318 | /* Deep-copy an IRConst */ |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 319 | extern IRConst* deepCopyIRConst ( IRConst* ); |
sewardj | 695cff9 | 2004-10-13 14:50:14 +0000 | [diff] [blame] | 320 | |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 321 | /* Pretty-print an IRConst */ |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 322 | extern void ppIRConst ( IRConst* ); |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 323 | |
| 324 | /* Compare two IRConsts for equality */ |
sewardj | 4345f7a | 2004-09-22 19:49:27 +0000 | [diff] [blame] | 325 | extern Bool eqIRConst ( IRConst*, IRConst* ); |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 326 | |
| 327 | |
sewardj | 8ea867b | 2004-10-30 19:03:02 +0000 | [diff] [blame] | 328 | /* ------------------ Call targets ------------------ */ |
| 329 | |
| 330 | /* Describes a helper function to call. The name part is purely for |
sewardj | 7735254 | 2004-10-30 20:39:01 +0000 | [diff] [blame] | 331 | pretty printing and not actually used. regparms=n tells the back |
sewardj | 8ea867b | 2004-10-30 19:03:02 +0000 | [diff] [blame] | 332 | end that the callee has been declared |
sewardj | 03d9114 | 2011-03-14 12:35:18 +0000 | [diff] [blame] | 333 | "__attribute__((regparm(n)))", although indirectly using the |
| 334 | VEX_REGPARM(n) macro. On some targets (x86) the back end will need |
| 335 | to construct a non-standard sequence to call a function declared |
| 336 | like this. |
sewardj | 43c5646 | 2004-11-06 12:17:57 +0000 | [diff] [blame] | 337 | |
| 338 | mcx_mask is a sop to Memcheck. It indicates which args should be |
| 339 | considered 'always defined' when lazily computing definedness of |
| 340 | the result. Bit 0 of mcx_mask corresponds to args[0], bit 1 to |
| 341 | args[1], etc. If a bit is set, the corresponding arg is excluded |
| 342 | (hence "x" in "mcx") from definedness checking. |
| 343 | */ |
sewardj | 8ea867b | 2004-10-30 19:03:02 +0000 | [diff] [blame] | 344 | |
| 345 | typedef |
| 346 | struct { |
florian | 1ff4756 | 2012-10-21 02:09:51 +0000 | [diff] [blame] | 347 | Int regparms; |
| 348 | const HChar* name; |
| 349 | void* addr; |
| 350 | UInt mcx_mask; |
sewardj | 8ea867b | 2004-10-30 19:03:02 +0000 | [diff] [blame] | 351 | } |
| 352 | IRCallee; |
| 353 | |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 354 | /* Create an IRCallee. */ |
florian | 1ff4756 | 2012-10-21 02:09:51 +0000 | [diff] [blame] | 355 | extern IRCallee* mkIRCallee ( Int regparms, const HChar* name, void* addr ); |
sewardj | 8ea867b | 2004-10-30 19:03:02 +0000 | [diff] [blame] | 356 | |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 357 | /* Deep-copy an IRCallee. */ |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 358 | extern IRCallee* deepCopyIRCallee ( IRCallee* ); |
sewardj | 8ea867b | 2004-10-30 19:03:02 +0000 | [diff] [blame] | 359 | |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 360 | /* Pretty-print an IRCallee. */ |
sewardj | 8ea867b | 2004-10-30 19:03:02 +0000 | [diff] [blame] | 361 | extern void ppIRCallee ( IRCallee* ); |
| 362 | |
| 363 | |
sewardj | 2d3f77c | 2004-09-22 23:49:09 +0000 | [diff] [blame] | 364 | /* ------------------ Guest state arrays ------------------ */ |
| 365 | |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 366 | /* This describes a section of the guest state that we want to |
| 367 | be able to index at run time, so as to be able to describe |
| 368 | indexed or rotating register files on the guest. */ |
sewardj | 2d3f77c | 2004-09-22 23:49:09 +0000 | [diff] [blame] | 369 | typedef |
| 370 | struct { |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 371 | Int base; /* guest state offset of start of indexed area */ |
| 372 | IRType elemTy; /* type of each element in the indexed area */ |
| 373 | Int nElems; /* number of elements in the indexed area */ |
sewardj | 2d3f77c | 2004-09-22 23:49:09 +0000 | [diff] [blame] | 374 | } |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 375 | IRRegArray; |
sewardj | 2d3f77c | 2004-09-22 23:49:09 +0000 | [diff] [blame] | 376 | |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 377 | extern IRRegArray* mkIRRegArray ( Int, IRType, Int ); |
sewardj | 2d3f77c | 2004-09-22 23:49:09 +0000 | [diff] [blame] | 378 | |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 379 | extern IRRegArray* deepCopyIRRegArray ( IRRegArray* ); |
sewardj | 695cff9 | 2004-10-13 14:50:14 +0000 | [diff] [blame] | 380 | |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 381 | extern void ppIRRegArray ( IRRegArray* ); |
| 382 | extern Bool eqIRRegArray ( IRRegArray*, IRRegArray* ); |
sewardj | 2d3f77c | 2004-09-22 23:49:09 +0000 | [diff] [blame] | 383 | |
| 384 | |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 385 | /* ------------------ Temporaries ------------------ */ |
sewardj | ec6ad59 | 2004-06-20 12:26:53 +0000 | [diff] [blame] | 386 | |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 387 | /* This represents a temporary, eg. t1. The IR optimiser relies on the |
| 388 | fact that IRTemps are 32-bit ints. Do not change them to be ints of |
| 389 | any other size. */ |
sewardj | fbcaf33 | 2004-07-08 01:46:01 +0000 | [diff] [blame] | 390 | typedef UInt IRTemp; |
sewardj | ec6ad59 | 2004-06-20 12:26:53 +0000 | [diff] [blame] | 391 | |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 392 | /* Pretty-print an IRTemp. */ |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 393 | extern void ppIRTemp ( IRTemp ); |
sewardj | ec6ad59 | 2004-06-20 12:26:53 +0000 | [diff] [blame] | 394 | |
sewardj | 92d168d | 2004-11-15 14:22:12 +0000 | [diff] [blame] | 395 | #define IRTemp_INVALID ((IRTemp)0xFFFFFFFF) |
sewardj | fbcaf33 | 2004-07-08 01:46:01 +0000 | [diff] [blame] | 396 | |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 397 | |
sewardj | 40c8026 | 2006-02-08 19:30:46 +0000 | [diff] [blame] | 398 | /* --------------- Primops (arity 1,2,3 and 4) --------------- */ |
sewardj | ec6ad59 | 2004-06-20 12:26:53 +0000 | [diff] [blame] | 399 | |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 400 | /* Primitive operations that are used in Unop, Binop, Triop and Qop |
| 401 | IRExprs. Once we take into account integer, floating point and SIMD |
| 402 | operations of all the different sizes, there are quite a lot of them. |
| 403 | Most instructions supported by the architectures that Vex supports |
| 404 | (x86, PPC, etc) are represented. Some more obscure ones (eg. cpuid) |
| 405 | are not; they are instead handled with dirty helpers that emulate |
| 406 | their functionality. Such obscure ones are thus not directly visible |
| 407 | in the IR, but their effects on guest state (memory and registers) |
| 408 | are made visible via the annotations in IRDirty structures. |
| 409 | */ |
sewardj | ac6b712 | 2004-06-27 01:03:57 +0000 | [diff] [blame] | 410 | typedef |
sewardj | 41f43bc | 2004-07-08 14:23:22 +0000 | [diff] [blame] | 411 | enum { |
sewardj | 71a35e7 | 2005-05-03 12:20:15 +0000 | [diff] [blame] | 412 | /* -- Do not change this ordering. The IR generators rely on |
| 413 | (eg) Iop_Add64 == IopAdd8 + 3. -- */ |
| 414 | |
sewardj | cfe046e | 2013-01-17 14:23:53 +0000 | [diff] [blame] | 415 | Iop_INVALID=0x1400, |
sewardj | 66de227 | 2004-07-16 21:19:05 +0000 | [diff] [blame] | 416 | Iop_Add8, Iop_Add16, Iop_Add32, Iop_Add64, |
sewardj | 41f43bc | 2004-07-08 14:23:22 +0000 | [diff] [blame] | 417 | Iop_Sub8, Iop_Sub16, Iop_Sub32, Iop_Sub64, |
sewardj | 41f43bc | 2004-07-08 14:23:22 +0000 | [diff] [blame] | 418 | /* Signless mul. MullS/MullU is elsewhere. */ |
| 419 | Iop_Mul8, Iop_Mul16, Iop_Mul32, Iop_Mul64, |
| 420 | Iop_Or8, Iop_Or16, Iop_Or32, Iop_Or64, |
| 421 | Iop_And8, Iop_And16, Iop_And32, Iop_And64, |
| 422 | Iop_Xor8, Iop_Xor16, Iop_Xor32, Iop_Xor64, |
| 423 | Iop_Shl8, Iop_Shl16, Iop_Shl32, Iop_Shl64, |
| 424 | Iop_Shr8, Iop_Shr16, Iop_Shr32, Iop_Shr64, |
| 425 | Iop_Sar8, Iop_Sar16, Iop_Sar32, Iop_Sar64, |
sewardj | e90ad6a | 2004-07-10 19:02:10 +0000 | [diff] [blame] | 426 | /* Integer comparisons. */ |
| 427 | Iop_CmpEQ8, Iop_CmpEQ16, Iop_CmpEQ32, Iop_CmpEQ64, |
| 428 | Iop_CmpNE8, Iop_CmpNE16, Iop_CmpNE32, Iop_CmpNE64, |
sewardj | 41f43bc | 2004-07-08 14:23:22 +0000 | [diff] [blame] | 429 | /* Tags for unary ops */ |
| 430 | Iop_Not8, Iop_Not16, Iop_Not32, Iop_Not64, |
sewardj | 71a35e7 | 2005-05-03 12:20:15 +0000 | [diff] [blame] | 431 | |
sewardj | 1fb8c92 | 2009-07-12 12:56:53 +0000 | [diff] [blame] | 432 | /* Exactly like CmpEQ8/16/32/64, but carrying the additional |
| 433 | hint that these compute the success/failure of a CAS |
| 434 | operation, and hence are almost certainly applied to two |
| 435 | copies of the same value, which in turn has implications for |
| 436 | Memcheck's instrumentation. */ |
| 437 | Iop_CasCmpEQ8, Iop_CasCmpEQ16, Iop_CasCmpEQ32, Iop_CasCmpEQ64, |
| 438 | Iop_CasCmpNE8, Iop_CasCmpNE16, Iop_CasCmpNE32, Iop_CasCmpNE64, |
| 439 | |
sewardj | e13074c | 2012-11-08 10:57:08 +0000 | [diff] [blame] | 440 | /* Exactly like CmpNE8/16/32/64, but carrying the additional |
| 441 | hint that these needs expensive definedness tracking. */ |
| 442 | Iop_ExpCmpNE8, Iop_ExpCmpNE16, Iop_ExpCmpNE32, Iop_ExpCmpNE64, |
| 443 | |
sewardj | 71a35e7 | 2005-05-03 12:20:15 +0000 | [diff] [blame] | 444 | /* -- Ordering not important after here. -- */ |
| 445 | |
sewardj | 9690d92 | 2004-07-14 01:39:17 +0000 | [diff] [blame] | 446 | /* Widening multiplies */ |
sewardj | 9b96767 | 2005-02-08 11:13:09 +0000 | [diff] [blame] | 447 | Iop_MullS8, Iop_MullS16, Iop_MullS32, Iop_MullS64, |
| 448 | Iop_MullU8, Iop_MullU16, Iop_MullU32, Iop_MullU64, |
sewardj | 8f3debf | 2004-09-08 23:42:23 +0000 | [diff] [blame] | 449 | |
sewardj | ce646f2 | 2004-08-31 23:55:54 +0000 | [diff] [blame] | 450 | /* Wierdo integer stuff */ |
sewardj | f53b735 | 2005-04-06 20:01:56 +0000 | [diff] [blame] | 451 | Iop_Clz64, Iop_Clz32, /* count leading zeroes */ |
| 452 | Iop_Ctz64, Iop_Ctz32, /* count trailing zeros */ |
| 453 | /* Ctz64/Ctz32/Clz64/Clz32 are UNDEFINED when given arguments of |
| 454 | zero. You must ensure they are never given a zero argument. |
sewardj | 8f3debf | 2004-09-08 23:42:23 +0000 | [diff] [blame] | 455 | */ |
| 456 | |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 457 | /* Standard integer comparisons */ |
sewardj | 9854007 | 2005-04-26 01:52:01 +0000 | [diff] [blame] | 458 | Iop_CmpLT32S, Iop_CmpLT64S, |
| 459 | Iop_CmpLE32S, Iop_CmpLE64S, |
| 460 | Iop_CmpLT32U, Iop_CmpLT64U, |
| 461 | Iop_CmpLE32U, Iop_CmpLE64U, |
sewardj | 343b9d0 | 2005-01-31 18:08:45 +0000 | [diff] [blame] | 462 | |
sewardj | 0033ddc | 2005-04-26 23:34:34 +0000 | [diff] [blame] | 463 | /* As a sop to Valgrind-Memcheck, the following are useful. */ |
| 464 | Iop_CmpNEZ8, Iop_CmpNEZ16, Iop_CmpNEZ32, Iop_CmpNEZ64, |
sewardj | eb17e49 | 2007-08-25 23:07:44 +0000 | [diff] [blame] | 465 | Iop_CmpwNEZ32, Iop_CmpwNEZ64, /* all-0s -> all-Os; other -> all-1s */ |
| 466 | Iop_Left8, Iop_Left16, Iop_Left32, Iop_Left64, /* \x -> x | -x */ |
sewardj | 478646f | 2008-05-01 20:13:04 +0000 | [diff] [blame] | 467 | Iop_Max32U, /* unsigned max */ |
sewardj | 0033ddc | 2005-04-26 23:34:34 +0000 | [diff] [blame] | 468 | |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 469 | /* PowerPC-style 3-way integer comparisons. Without them it is |
| 470 | difficult to simulate PPC efficiently. |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 471 | op(x,y) | x < y = 0x8 else |
| 472 | | x > y = 0x4 else |
| 473 | | x == y = 0x2 |
| 474 | */ |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 475 | Iop_CmpORD32U, Iop_CmpORD64U, |
| 476 | Iop_CmpORD32S, Iop_CmpORD64S, |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 477 | |
sewardj | 9690d92 | 2004-07-14 01:39:17 +0000 | [diff] [blame] | 478 | /* Division */ |
sewardj | 8f3debf | 2004-09-08 23:42:23 +0000 | [diff] [blame] | 479 | /* TODO: clarify semantics wrt rounding, negative values, whatever */ |
cerion | 5c8a0cb | 2005-02-03 13:59:46 +0000 | [diff] [blame] | 480 | Iop_DivU32, // :: I32,I32 -> I32 (simple div, no mod) |
| 481 | Iop_DivS32, // ditto, signed |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 482 | Iop_DivU64, // :: I64,I64 -> I64 (simple div, no mod) |
| 483 | Iop_DivS64, // ditto, signed |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 484 | Iop_DivU64E, // :: I64,I64 -> I64 (dividend is 64-bit arg (hi) concat with 64 0's (low)) |
| 485 | Iop_DivS64E, // ditto, signed |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 486 | Iop_DivU32E, // :: I32,I32 -> I32 (dividend is 32-bit arg (hi) concat with 32 0's (low)) |
sewardj | e71e56a | 2011-09-05 12:11:06 +0000 | [diff] [blame] | 487 | Iop_DivS32E, // ditto, signed |
cerion | 5c8a0cb | 2005-02-03 13:59:46 +0000 | [diff] [blame] | 488 | |
sewardj | 9690d92 | 2004-07-14 01:39:17 +0000 | [diff] [blame] | 489 | Iop_DivModU64to32, // :: I64,I32 -> I64 |
| 490 | // of which lo half is div and hi half is mod |
| 491 | Iop_DivModS64to32, // ditto, signed |
sewardj | 89d4e98 | 2004-09-12 19:14:46 +0000 | [diff] [blame] | 492 | |
sewardj | 343b9d0 | 2005-01-31 18:08:45 +0000 | [diff] [blame] | 493 | Iop_DivModU128to64, // :: V128,I64 -> V128 |
| 494 | // of which lo half is div and hi half is mod |
| 495 | Iop_DivModS128to64, // ditto, signed |
| 496 | |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 497 | Iop_DivModS64to64, // :: I64,I64 -> I128 |
| 498 | // of which lo half is div and hi half is mod |
| 499 | |
sewardj | 0033ddc | 2005-04-26 23:34:34 +0000 | [diff] [blame] | 500 | /* Integer conversions. Some of these are redundant (eg |
| 501 | Iop_64to8 is the same as Iop_64to32 and then Iop_32to8), but |
| 502 | having a complete set reduces the typical dynamic size of IR |
| 503 | and makes the instruction selectors easier to write. */ |
| 504 | |
sewardj | 9690d92 | 2004-07-14 01:39:17 +0000 | [diff] [blame] | 505 | /* Widening conversions */ |
sewardj | 0033ddc | 2005-04-26 23:34:34 +0000 | [diff] [blame] | 506 | Iop_8Uto16, Iop_8Uto32, Iop_8Uto64, |
| 507 | Iop_16Uto32, Iop_16Uto64, |
| 508 | Iop_32Uto64, |
| 509 | Iop_8Sto16, Iop_8Sto32, Iop_8Sto64, |
| 510 | Iop_16Sto32, Iop_16Sto64, |
| 511 | Iop_32Sto64, |
| 512 | |
sewardj | a238471 | 2004-07-29 14:36:40 +0000 | [diff] [blame] | 513 | /* Narrowing conversions */ |
sewardj | 0033ddc | 2005-04-26 23:34:34 +0000 | [diff] [blame] | 514 | Iop_64to8, Iop_32to8, Iop_64to16, |
sewardj | b81f8b3 | 2004-07-30 10:17:50 +0000 | [diff] [blame] | 515 | /* 8 <-> 16 bit conversions */ |
| 516 | Iop_16to8, // :: I16 -> I8, low half |
| 517 | Iop_16HIto8, // :: I16 -> I8, high half |
| 518 | Iop_8HLto16, // :: (I8,I8) -> I16 |
sewardj | 8c7f1ab | 2004-07-29 20:31:09 +0000 | [diff] [blame] | 519 | /* 16 <-> 32 bit conversions */ |
| 520 | Iop_32to16, // :: I32 -> I16, low half |
| 521 | Iop_32HIto16, // :: I32 -> I16, high half |
| 522 | Iop_16HLto32, // :: (I16,I16) -> I32 |
sewardj | 9690d92 | 2004-07-14 01:39:17 +0000 | [diff] [blame] | 523 | /* 32 <-> 64 bit conversions */ |
sewardj | 8c7f1ab | 2004-07-29 20:31:09 +0000 | [diff] [blame] | 524 | Iop_64to32, // :: I64 -> I32, low half |
sewardj | 9690d92 | 2004-07-14 01:39:17 +0000 | [diff] [blame] | 525 | Iop_64HIto32, // :: I64 -> I32, high half |
| 526 | Iop_32HLto64, // :: (I32,I32) -> I64 |
sewardj | 9b96767 | 2005-02-08 11:13:09 +0000 | [diff] [blame] | 527 | /* 64 <-> 128 bit conversions */ |
| 528 | Iop_128to64, // :: I128 -> I64, low half |
| 529 | Iop_128HIto64, // :: I128 -> I64, high half |
| 530 | Iop_64HLto128, // :: (I64,I64) -> I128 |
sewardj | cf780b4 | 2004-07-13 18:42:17 +0000 | [diff] [blame] | 531 | /* 1-bit stuff */ |
sewardj | 6e797c5 | 2004-10-13 15:20:17 +0000 | [diff] [blame] | 532 | Iop_Not1, /* :: Ity_Bit -> Ity_Bit */ |
sewardj | 84ff065 | 2004-08-23 16:16:08 +0000 | [diff] [blame] | 533 | Iop_32to1, /* :: Ity_I32 -> Ity_Bit, just select bit[0] */ |
sewardj | 291a7e8 | 2005-04-27 11:42:44 +0000 | [diff] [blame] | 534 | Iop_64to1, /* :: Ity_I64 -> Ity_Bit, just select bit[0] */ |
| 535 | Iop_1Uto8, /* :: Ity_Bit -> Ity_I8, unsigned widen */ |
sewardj | 84ff065 | 2004-08-23 16:16:08 +0000 | [diff] [blame] | 536 | Iop_1Uto32, /* :: Ity_Bit -> Ity_I32, unsigned widen */ |
sewardj | 291a7e8 | 2005-04-27 11:42:44 +0000 | [diff] [blame] | 537 | Iop_1Uto64, /* :: Ity_Bit -> Ity_I64, unsigned widen */ |
sewardj | fd33277 | 2004-11-09 16:01:40 +0000 | [diff] [blame] | 538 | Iop_1Sto8, /* :: Ity_Bit -> Ity_I8, signed widen */ |
sewardj | 8eda630 | 2004-11-05 01:55:46 +0000 | [diff] [blame] | 539 | Iop_1Sto16, /* :: Ity_Bit -> Ity_I16, signed widen */ |
sewardj | cf78790 | 2004-11-03 09:08:33 +0000 | [diff] [blame] | 540 | Iop_1Sto32, /* :: Ity_Bit -> Ity_I32, signed widen */ |
sewardj | b5874aa | 2004-11-04 16:57:50 +0000 | [diff] [blame] | 541 | Iop_1Sto64, /* :: Ity_Bit -> Ity_I64, signed widen */ |
sewardj | 8f3debf | 2004-09-08 23:42:23 +0000 | [diff] [blame] | 542 | |
sewardj | baf971a | 2006-01-27 15:09:35 +0000 | [diff] [blame] | 543 | /* ------ Floating point. We try to be IEEE754 compliant. ------ */ |
sewardj | 8f3debf | 2004-09-08 23:42:23 +0000 | [diff] [blame] | 544 | |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 545 | /* --- Simple stuff as mandated by 754. --- */ |
sewardj | cfded9a | 2004-09-09 11:44:16 +0000 | [diff] [blame] | 546 | |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 547 | /* Binary operations, with rounding. */ |
| 548 | /* :: IRRoundingMode(I32) x F64 x F64 -> F64 */ |
| 549 | Iop_AddF64, Iop_SubF64, Iop_MulF64, Iop_DivF64, |
sewardj | 52ace3e | 2004-09-11 17:10:08 +0000 | [diff] [blame] | 550 | |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 551 | /* :: IRRoundingMode(I32) x F32 x F32 -> F32 */ |
| 552 | Iop_AddF32, Iop_SubF32, Iop_MulF32, Iop_DivF32, |
| 553 | |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 554 | /* Variants of the above which produce a 64-bit result but which |
| 555 | round their result to a IEEE float range first. */ |
| 556 | /* :: IRRoundingMode(I32) x F64 x F64 -> F64 */ |
| 557 | Iop_AddF64r32, Iop_SubF64r32, Iop_MulF64r32, Iop_DivF64r32, |
sewardj | 52ace3e | 2004-09-11 17:10:08 +0000 | [diff] [blame] | 558 | |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 559 | /* Unary operations, without rounding. */ |
| 560 | /* :: F64 -> F64 */ |
| 561 | Iop_NegF64, Iop_AbsF64, |
sewardj | 8f3debf | 2004-09-08 23:42:23 +0000 | [diff] [blame] | 562 | |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 563 | /* :: F32 -> F32 */ |
| 564 | Iop_NegF32, Iop_AbsF32, |
| 565 | |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 566 | /* Unary operations, with rounding. */ |
| 567 | /* :: IRRoundingMode(I32) x F64 -> F64 */ |
florian | 6d52228 | 2012-08-21 22:15:19 +0000 | [diff] [blame] | 568 | Iop_SqrtF64, |
sewardj | baf971a | 2006-01-27 15:09:35 +0000 | [diff] [blame] | 569 | |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 570 | /* :: IRRoundingMode(I32) x F32 -> F32 */ |
| 571 | Iop_SqrtF32, |
| 572 | |
sewardj | 8f3debf | 2004-09-08 23:42:23 +0000 | [diff] [blame] | 573 | /* Comparison, yielding GT/LT/EQ/UN(ordered), as per the following: |
sewardj | 883b00b | 2004-09-11 09:30:24 +0000 | [diff] [blame] | 574 | 0x45 Unordered |
sewardj | 8f3debf | 2004-09-08 23:42:23 +0000 | [diff] [blame] | 575 | 0x01 LT |
| 576 | 0x00 GT |
sewardj | 883b00b | 2004-09-11 09:30:24 +0000 | [diff] [blame] | 577 | 0x40 EQ |
sewardj | 8f3debf | 2004-09-08 23:42:23 +0000 | [diff] [blame] | 578 | This just happens to be the Intel encoding. The values |
| 579 | are recorded in the type IRCmpF64Result. |
| 580 | */ |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 581 | /* :: F64 x F64 -> IRCmpF64Result(I32) */ |
sewardj | 8f3debf | 2004-09-08 23:42:23 +0000 | [diff] [blame] | 582 | Iop_CmpF64, |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 583 | Iop_CmpF32, |
| 584 | Iop_CmpF128, |
sewardj | 8f3debf | 2004-09-08 23:42:23 +0000 | [diff] [blame] | 585 | |
sewardj | 3bca906 | 2004-12-04 14:36:09 +0000 | [diff] [blame] | 586 | /* --- Int to/from FP conversions. --- */ |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 587 | |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 588 | /* For the most part, these take a first argument :: Ity_I32 (as |
| 589 | IRRoundingMode) which is an indication of the rounding mode |
| 590 | to use, as per the following encoding ("the standard |
| 591 | encoding"): |
sewardj | 8f3debf | 2004-09-08 23:42:23 +0000 | [diff] [blame] | 592 | 00b to nearest (the default) |
| 593 | 01b to -infinity |
| 594 | 10b to +infinity |
| 595 | 11b to zero |
| 596 | This just happens to be the Intel encoding. For reference only, |
| 597 | the PPC encoding is: |
| 598 | 00b to nearest (the default) |
| 599 | 01b to zero |
| 600 | 10b to +infinity |
| 601 | 11b to -infinity |
| 602 | Any PPC -> IR front end will have to translate these PPC |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 603 | encodings, as encoded in the guest state, to the standard |
| 604 | encodings, to pass to the primops. |
| 605 | For reference only, the ARM VFP encoding is: |
| 606 | 00b to nearest |
| 607 | 01b to +infinity |
| 608 | 10b to -infinity |
| 609 | 11b to zero |
| 610 | Again, this will have to be converted to the standard encoding |
| 611 | to pass to primops. |
sewardj | 8f3debf | 2004-09-08 23:42:23 +0000 | [diff] [blame] | 612 | |
| 613 | If one of these conversions gets an out-of-range condition, |
| 614 | or a NaN, as an argument, the result is host-defined. On x86 |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 615 | the "integer indefinite" value 0x80..00 is produced. On PPC |
| 616 | it is either 0x80..00 or 0x7F..FF depending on the sign of |
| 617 | the argument. |
| 618 | |
| 619 | On ARMvfp, when converting to a signed integer result, the |
| 620 | overflow result is 0x80..00 for negative args and 0x7F..FF |
| 621 | for positive args. For unsigned integer results it is |
| 622 | 0x00..00 and 0xFF..FF respectively. |
sewardj | 52ace3e | 2004-09-11 17:10:08 +0000 | [diff] [blame] | 623 | |
sewardj | 3bca906 | 2004-12-04 14:36:09 +0000 | [diff] [blame] | 624 | Rounding is required whenever the destination type cannot |
| 625 | represent exactly all values of the source type. |
| 626 | */ |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 627 | Iop_F64toI16S, /* IRRoundingMode(I32) x F64 -> signed I16 */ |
| 628 | Iop_F64toI32S, /* IRRoundingMode(I32) x F64 -> signed I32 */ |
| 629 | Iop_F64toI64S, /* IRRoundingMode(I32) x F64 -> signed I64 */ |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 630 | Iop_F64toI64U, /* IRRoundingMode(I32) x F64 -> unsigned I64 */ |
sewardj | 3bca906 | 2004-12-04 14:36:09 +0000 | [diff] [blame] | 631 | |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 632 | Iop_F64toI32U, /* IRRoundingMode(I32) x F64 -> unsigned I32 */ |
sewardj | 3bca906 | 2004-12-04 14:36:09 +0000 | [diff] [blame] | 633 | |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 634 | Iop_I32StoF64, /* signed I32 -> F64 */ |
| 635 | Iop_I64StoF64, /* IRRoundingMode(I32) x signed I64 -> F64 */ |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 636 | Iop_I64UtoF64, /* IRRoundingMode(I32) x unsigned I64 -> F64 */ |
| 637 | Iop_I64UtoF32, /* IRRoundingMode(I32) x unsigned I64 -> F32 */ |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 638 | |
florian | 1c8f7ff | 2012-09-01 00:12:11 +0000 | [diff] [blame] | 639 | Iop_I32UtoF32, /* IRRoundingMode(I32) x unsigned I32 -> F32 */ |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 640 | Iop_I32UtoF64, /* unsigned I32 -> F64 */ |
| 641 | |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 642 | Iop_F32toI32S, /* IRRoundingMode(I32) x F32 -> signed I32 */ |
| 643 | Iop_F32toI64S, /* IRRoundingMode(I32) x F32 -> signed I64 */ |
florian | 1c8f7ff | 2012-09-01 00:12:11 +0000 | [diff] [blame] | 644 | Iop_F32toI32U, /* IRRoundingMode(I32) x F32 -> unsigned I32 */ |
| 645 | Iop_F32toI64U, /* IRRoundingMode(I32) x F32 -> unsigned I64 */ |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 646 | |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 647 | Iop_I32StoF32, /* IRRoundingMode(I32) x signed I32 -> F32 */ |
| 648 | Iop_I64StoF32, /* IRRoundingMode(I32) x signed I64 -> F32 */ |
| 649 | |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 650 | /* Conversion between floating point formats */ |
sewardj | 3bca906 | 2004-12-04 14:36:09 +0000 | [diff] [blame] | 651 | Iop_F32toF64, /* F32 -> F64 */ |
| 652 | Iop_F64toF32, /* IRRoundingMode(I32) x F64 -> F32 */ |
sewardj | 4cb918d | 2004-12-03 19:43:31 +0000 | [diff] [blame] | 653 | |
sewardj | 17442fe | 2004-09-20 14:54:28 +0000 | [diff] [blame] | 654 | /* Reinterpretation. Take an F64 and produce an I64 with |
| 655 | the same bit pattern, or vice versa. */ |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 656 | Iop_ReinterpF64asI64, Iop_ReinterpI64asF64, |
sewardj | fc1b541 | 2007-01-09 15:20:07 +0000 | [diff] [blame] | 657 | Iop_ReinterpF32asI32, Iop_ReinterpI32asF32, |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 658 | |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 659 | /* Support for 128-bit floating point */ |
| 660 | Iop_F64HLtoF128,/* (high half of F128,low half of F128) -> F128 */ |
| 661 | Iop_F128HItoF64,/* F128 -> high half of F128 into a F64 register */ |
| 662 | Iop_F128LOtoF64,/* F128 -> low half of F128 into a F64 register */ |
| 663 | |
| 664 | /* :: IRRoundingMode(I32) x F128 x F128 -> F128 */ |
| 665 | Iop_AddF128, Iop_SubF128, Iop_MulF128, Iop_DivF128, |
| 666 | |
| 667 | /* :: F128 -> F128 */ |
| 668 | Iop_NegF128, Iop_AbsF128, |
| 669 | |
| 670 | /* :: IRRoundingMode(I32) x F128 -> F128 */ |
| 671 | Iop_SqrtF128, |
| 672 | |
| 673 | Iop_I32StoF128, /* signed I32 -> F128 */ |
| 674 | Iop_I64StoF128, /* signed I64 -> F128 */ |
florian | 1c8f7ff | 2012-09-01 00:12:11 +0000 | [diff] [blame] | 675 | Iop_I32UtoF128, /* unsigned I32 -> F128 */ |
| 676 | Iop_I64UtoF128, /* unsigned I64 -> F128 */ |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 677 | Iop_F32toF128, /* F32 -> F128 */ |
| 678 | Iop_F64toF128, /* F64 -> F128 */ |
| 679 | |
| 680 | Iop_F128toI32S, /* IRRoundingMode(I32) x F128 -> signed I32 */ |
| 681 | Iop_F128toI64S, /* IRRoundingMode(I32) x F128 -> signed I64 */ |
florian | 1c8f7ff | 2012-09-01 00:12:11 +0000 | [diff] [blame] | 682 | Iop_F128toI32U, /* IRRoundingMode(I32) x F128 -> unsigned I32 */ |
| 683 | Iop_F128toI64U, /* IRRoundingMode(I32) x F128 -> unsigned I64 */ |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 684 | Iop_F128toF64, /* IRRoundingMode(I32) x F128 -> F64 */ |
| 685 | Iop_F128toF32, /* IRRoundingMode(I32) x F128 -> F32 */ |
| 686 | |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 687 | /* --- guest x86/amd64 specifics, not mandated by 754. --- */ |
| 688 | |
| 689 | /* Binary ops, with rounding. */ |
| 690 | /* :: IRRoundingMode(I32) x F64 x F64 -> F64 */ |
| 691 | Iop_AtanF64, /* FPATAN, arctan(arg1/arg2) */ |
| 692 | Iop_Yl2xF64, /* FYL2X, arg1 * log2(arg2) */ |
| 693 | Iop_Yl2xp1F64, /* FYL2XP1, arg1 * log2(arg2+1.0) */ |
| 694 | Iop_PRemF64, /* FPREM, non-IEEE remainder(arg1/arg2) */ |
| 695 | Iop_PRemC3210F64, /* C3210 flags resulting from FPREM, :: I32 */ |
| 696 | Iop_PRem1F64, /* FPREM1, IEEE remainder(arg1/arg2) */ |
| 697 | Iop_PRem1C3210F64, /* C3210 flags resulting from FPREM1, :: I32 */ |
| 698 | Iop_ScaleF64, /* FSCALE, arg1 * (2^RoundTowardsZero(arg2)) */ |
| 699 | /* Note that on x86 guest, PRem1{C3210} has the same behaviour |
| 700 | as the IEEE mandated RemF64, except it is limited in the |
| 701 | range of its operand. Hence the partialness. */ |
| 702 | |
| 703 | /* Unary ops, with rounding. */ |
| 704 | /* :: IRRoundingMode(I32) x F64 -> F64 */ |
| 705 | Iop_SinF64, /* FSIN */ |
| 706 | Iop_CosF64, /* FCOS */ |
| 707 | Iop_TanF64, /* FTAN */ |
| 708 | Iop_2xm1F64, /* (2^arg - 1.0) */ |
| 709 | Iop_RoundF64toInt, /* F64 value to nearest integral value (still |
| 710 | as F64) */ |
sewardj | d15b597 | 2010-06-27 09:06:34 +0000 | [diff] [blame] | 711 | Iop_RoundF32toInt, /* F32 value to nearest integral value (still |
| 712 | as F32) */ |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 713 | |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 714 | /* --- guest s390 specifics, not mandated by 754. --- */ |
| 715 | |
| 716 | /* Fused multiply-add/sub */ |
| 717 | /* :: IRRoundingMode(I32) x F32 x F32 x F32 -> F32 |
florian | 5906a6b | 2012-10-16 02:53:33 +0000 | [diff] [blame] | 718 | (computes arg2 * arg3 +/- arg4) */ |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 719 | Iop_MAddF32, Iop_MSubF32, |
| 720 | |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 721 | /* --- guest ppc32/64 specifics, not mandated by 754. --- */ |
| 722 | |
sewardj | 40c8026 | 2006-02-08 19:30:46 +0000 | [diff] [blame] | 723 | /* Ternary operations, with rounding. */ |
| 724 | /* Fused multiply-add/sub, with 112-bit intermediate |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 725 | precision for ppc. |
| 726 | Also used to implement fused multiply-add/sub for s390. */ |
sewardj | 40c8026 | 2006-02-08 19:30:46 +0000 | [diff] [blame] | 727 | /* :: IRRoundingMode(I32) x F64 x F64 x F64 -> F64 |
| 728 | (computes arg2 * arg3 +/- arg4) */ |
| 729 | Iop_MAddF64, Iop_MSubF64, |
| 730 | |
| 731 | /* Variants of the above which produce a 64-bit result but which |
| 732 | round their result to a IEEE float range first. */ |
| 733 | /* :: IRRoundingMode(I32) x F64 x F64 x F64 -> F64 */ |
| 734 | Iop_MAddF64r32, Iop_MSubF64r32, |
| 735 | |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 736 | /* :: F64 -> F64 */ |
| 737 | Iop_Est5FRSqrt, /* reciprocal square root estimate, 5 good bits */ |
sewardj | 0f1ef86 | 2008-08-08 08:37:06 +0000 | [diff] [blame] | 738 | Iop_RoundF64toF64_NEAREST, /* frin */ |
| 739 | Iop_RoundF64toF64_NegINF, /* frim */ |
| 740 | Iop_RoundF64toF64_PosINF, /* frip */ |
| 741 | Iop_RoundF64toF64_ZERO, /* friz */ |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 742 | |
| 743 | /* :: F64 -> F32 */ |
| 744 | Iop_TruncF64asF32, /* do F64->F32 truncation as per 'fsts' */ |
| 745 | |
| 746 | /* :: IRRoundingMode(I32) x F64 -> F64 */ |
| 747 | Iop_RoundF64toF32, /* round F64 to nearest F32 value (still as F64) */ |
| 748 | /* NB: pretty much the same as Iop_F64toF32, except no change |
| 749 | of type. */ |
| 750 | |
sewardj | e2ea176 | 2010-09-22 00:56:37 +0000 | [diff] [blame] | 751 | /* ------------------ 32-bit SIMD Integer ------------------ */ |
| 752 | |
sewardj | 44ce46d | 2012-07-11 13:19:10 +0000 | [diff] [blame] | 753 | /* 32x1 saturating add/sub (ok, well, not really SIMD :) */ |
| 754 | Iop_QAdd32S, |
| 755 | Iop_QSub32S, |
| 756 | |
sewardj | e2ea176 | 2010-09-22 00:56:37 +0000 | [diff] [blame] | 757 | /* 16x2 add/sub, also signed/unsigned saturating variants */ |
| 758 | Iop_Add16x2, Iop_Sub16x2, |
| 759 | Iop_QAdd16Sx2, Iop_QAdd16Ux2, |
| 760 | Iop_QSub16Sx2, Iop_QSub16Ux2, |
| 761 | |
| 762 | /* 16x2 signed/unsigned halving add/sub. For each lane, these |
| 763 | compute bits 16:1 of (eg) sx(argL) + sx(argR), |
| 764 | or zx(argL) - zx(argR) etc. */ |
| 765 | Iop_HAdd16Ux2, Iop_HAdd16Sx2, |
| 766 | Iop_HSub16Ux2, Iop_HSub16Sx2, |
| 767 | |
| 768 | /* 8x4 add/sub, also signed/unsigned saturating variants */ |
| 769 | Iop_Add8x4, Iop_Sub8x4, |
| 770 | Iop_QAdd8Sx4, Iop_QAdd8Ux4, |
| 771 | Iop_QSub8Sx4, Iop_QSub8Ux4, |
| 772 | |
| 773 | /* 8x4 signed/unsigned halving add/sub. For each lane, these |
| 774 | compute bits 8:1 of (eg) sx(argL) + sx(argR), |
| 775 | or zx(argL) - zx(argR) etc. */ |
| 776 | Iop_HAdd8Ux4, Iop_HAdd8Sx4, |
| 777 | Iop_HSub8Ux4, Iop_HSub8Sx4, |
| 778 | |
sewardj | 310d6b2 | 2010-10-18 16:29:40 +0000 | [diff] [blame] | 779 | /* 8x4 sum of absolute unsigned differences. */ |
| 780 | Iop_Sad8Ux4, |
| 781 | |
sewardj | e2ea176 | 2010-09-22 00:56:37 +0000 | [diff] [blame] | 782 | /* MISC (vector integer cmp != 0) */ |
| 783 | Iop_CmpNEZ16x2, Iop_CmpNEZ8x4, |
| 784 | |
sewardj | 2fdd416 | 2010-08-22 12:59:02 +0000 | [diff] [blame] | 785 | /* ------------------ 64-bit SIMD FP ------------------------ */ |
| 786 | |
| 787 | /* Convertion to/from int */ |
| 788 | Iop_I32UtoFx2, Iop_I32StoFx2, /* I32x4 -> F32x4 */ |
| 789 | Iop_FtoI32Ux2_RZ, Iop_FtoI32Sx2_RZ, /* F32x4 -> I32x4 */ |
| 790 | /* Fixed32 format is floating-point number with fixed number of fraction |
| 791 | bits. The number of fraction bits is passed as a second argument of |
| 792 | type I8. */ |
| 793 | Iop_F32ToFixed32Ux2_RZ, Iop_F32ToFixed32Sx2_RZ, /* fp -> fixed-point */ |
| 794 | Iop_Fixed32UToF32x2_RN, Iop_Fixed32SToF32x2_RN, /* fixed-point -> fp */ |
| 795 | |
| 796 | /* Binary operations */ |
| 797 | Iop_Max32Fx2, Iop_Min32Fx2, |
| 798 | /* Pairwise Min and Max. See integer pairwise operations for more |
| 799 | details. */ |
| 800 | Iop_PwMax32Fx2, Iop_PwMin32Fx2, |
| 801 | /* Note: For the following compares, the arm front-end assumes a |
| 802 | nan in a lane of either argument returns zero for that lane. */ |
| 803 | Iop_CmpEQ32Fx2, Iop_CmpGT32Fx2, Iop_CmpGE32Fx2, |
| 804 | |
| 805 | /* Vector Reciprocal Estimate finds an approximate reciprocal of each |
| 806 | element in the operand vector, and places the results in the destination |
| 807 | vector. */ |
| 808 | Iop_Recip32Fx2, |
| 809 | |
| 810 | /* Vector Reciprocal Step computes (2.0 - arg1 * arg2). |
| 811 | Note, that if one of the arguments is zero and another one is infinity |
| 812 | of arbitrary sign the result of the operation is 2.0. */ |
| 813 | Iop_Recps32Fx2, |
| 814 | |
| 815 | /* Vector Reciprocal Square Root Estimate finds an approximate reciprocal |
| 816 | square root of each element in the operand vector. */ |
| 817 | Iop_Rsqrte32Fx2, |
| 818 | |
| 819 | /* Vector Reciprocal Square Root Step computes (3.0 - arg1 * arg2) / 2.0. |
| 820 | Note, that of one of the arguments is zero and another one is infiinty |
| 821 | of arbitrary sign the result of the operation is 1.5. */ |
| 822 | Iop_Rsqrts32Fx2, |
| 823 | |
| 824 | /* Unary */ |
| 825 | Iop_Neg32Fx2, Iop_Abs32Fx2, |
| 826 | |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 827 | /* ------------------ 64-bit SIMD Integer. ------------------ */ |
| 828 | |
| 829 | /* MISC (vector integer cmp != 0) */ |
sewardj | 1806918 | 2005-01-13 19:16:04 +0000 | [diff] [blame] | 830 | Iop_CmpNEZ8x8, Iop_CmpNEZ16x4, Iop_CmpNEZ32x2, |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 831 | |
| 832 | /* ADDITION (normal / unsigned sat / signed sat) */ |
| 833 | Iop_Add8x8, Iop_Add16x4, Iop_Add32x2, |
sewardj | 2fdd416 | 2010-08-22 12:59:02 +0000 | [diff] [blame] | 834 | Iop_QAdd8Ux8, Iop_QAdd16Ux4, Iop_QAdd32Ux2, Iop_QAdd64Ux1, |
| 835 | Iop_QAdd8Sx8, Iop_QAdd16Sx4, Iop_QAdd32Sx2, Iop_QAdd64Sx1, |
| 836 | |
| 837 | /* PAIRWISE operations */ |
| 838 | /* Iop_PwFoo16x4( [a,b,c,d], [e,f,g,h] ) = |
| 839 | [Foo16(a,b), Foo16(c,d), Foo16(e,f), Foo16(g,h)] */ |
| 840 | Iop_PwAdd8x8, Iop_PwAdd16x4, Iop_PwAdd32x2, |
| 841 | Iop_PwMax8Sx8, Iop_PwMax16Sx4, Iop_PwMax32Sx2, |
| 842 | Iop_PwMax8Ux8, Iop_PwMax16Ux4, Iop_PwMax32Ux2, |
| 843 | Iop_PwMin8Sx8, Iop_PwMin16Sx4, Iop_PwMin32Sx2, |
| 844 | Iop_PwMin8Ux8, Iop_PwMin16Ux4, Iop_PwMin32Ux2, |
| 845 | /* Longening variant is unary. The resulting vector contains two times |
| 846 | less elements than operand, but they are two times wider. |
| 847 | Example: |
| 848 | Iop_PAddL16Ux4( [a,b,c,d] ) = [a+b,c+d] |
| 849 | where a+b and c+d are unsigned 32-bit values. */ |
| 850 | Iop_PwAddL8Ux8, Iop_PwAddL16Ux4, Iop_PwAddL32Ux2, |
| 851 | Iop_PwAddL8Sx8, Iop_PwAddL16Sx4, Iop_PwAddL32Sx2, |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 852 | |
| 853 | /* SUBTRACTION (normal / unsigned sat / signed sat) */ |
| 854 | Iop_Sub8x8, Iop_Sub16x4, Iop_Sub32x2, |
sewardj | 2fdd416 | 2010-08-22 12:59:02 +0000 | [diff] [blame] | 855 | Iop_QSub8Ux8, Iop_QSub16Ux4, Iop_QSub32Ux2, Iop_QSub64Ux1, |
| 856 | Iop_QSub8Sx8, Iop_QSub16Sx4, Iop_QSub32Sx2, Iop_QSub64Sx1, |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 857 | |
sewardj | 2fdd416 | 2010-08-22 12:59:02 +0000 | [diff] [blame] | 858 | /* ABSOLUTE VALUE */ |
| 859 | Iop_Abs8x8, Iop_Abs16x4, Iop_Abs32x2, |
| 860 | |
| 861 | /* MULTIPLICATION (normal / high half of signed/unsigned / plynomial ) */ |
| 862 | Iop_Mul8x8, Iop_Mul16x4, Iop_Mul32x2, |
| 863 | Iop_Mul32Fx2, |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 864 | Iop_MulHi16Ux4, |
| 865 | Iop_MulHi16Sx4, |
sewardj | 2fdd416 | 2010-08-22 12:59:02 +0000 | [diff] [blame] | 866 | /* Plynomial multiplication treats it's arguments as coefficients of |
| 867 | polynoms over {0, 1}. */ |
| 868 | Iop_PolynomialMul8x8, |
| 869 | |
| 870 | /* Vector Saturating Doubling Multiply Returning High Half and |
| 871 | Vector Saturating Rounding Doubling Multiply Returning High Half */ |
| 872 | /* These IROp's multiply corresponding elements in two vectors, double |
| 873 | the results, and place the most significant half of the final results |
| 874 | in the destination vector. The results are truncated or rounded. If |
| 875 | any of the results overflow, they are saturated. */ |
| 876 | Iop_QDMulHi16Sx4, Iop_QDMulHi32Sx2, |
| 877 | Iop_QRDMulHi16Sx4, Iop_QRDMulHi32Sx2, |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 878 | |
sewardj | 5ce5fd6 | 2005-04-19 23:06:11 +0000 | [diff] [blame] | 879 | /* AVERAGING: note: (arg1 + arg2 + 1) >>u 1 */ |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 880 | Iop_Avg8Ux8, |
| 881 | Iop_Avg16Ux4, |
| 882 | |
| 883 | /* MIN/MAX */ |
sewardj | 2fdd416 | 2010-08-22 12:59:02 +0000 | [diff] [blame] | 884 | Iop_Max8Sx8, Iop_Max16Sx4, Iop_Max32Sx2, |
| 885 | Iop_Max8Ux8, Iop_Max16Ux4, Iop_Max32Ux2, |
| 886 | Iop_Min8Sx8, Iop_Min16Sx4, Iop_Min32Sx2, |
| 887 | Iop_Min8Ux8, Iop_Min16Ux4, Iop_Min32Ux2, |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 888 | |
| 889 | /* COMPARISON */ |
| 890 | Iop_CmpEQ8x8, Iop_CmpEQ16x4, Iop_CmpEQ32x2, |
sewardj | 2fdd416 | 2010-08-22 12:59:02 +0000 | [diff] [blame] | 891 | Iop_CmpGT8Ux8, Iop_CmpGT16Ux4, Iop_CmpGT32Ux2, |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 892 | Iop_CmpGT8Sx8, Iop_CmpGT16Sx4, Iop_CmpGT32Sx2, |
| 893 | |
sewardj | 2fdd416 | 2010-08-22 12:59:02 +0000 | [diff] [blame] | 894 | /* COUNT ones / leading zeroes / leading sign bits (not including topmost |
| 895 | bit) */ |
| 896 | Iop_Cnt8x8, |
| 897 | Iop_Clz8Sx8, Iop_Clz16Sx4, Iop_Clz32Sx2, |
| 898 | Iop_Cls8Sx8, Iop_Cls16Sx4, Iop_Cls32Sx2, |
| 899 | |
| 900 | /* VECTOR x VECTOR SHIFT / ROTATE */ |
| 901 | Iop_Shl8x8, Iop_Shl16x4, Iop_Shl32x2, |
| 902 | Iop_Shr8x8, Iop_Shr16x4, Iop_Shr32x2, |
| 903 | Iop_Sar8x8, Iop_Sar16x4, Iop_Sar32x2, |
| 904 | Iop_Sal8x8, Iop_Sal16x4, Iop_Sal32x2, Iop_Sal64x1, |
| 905 | |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 906 | /* VECTOR x SCALAR SHIFT (shift amt :: Ity_I8) */ |
sewardj | d166e28 | 2008-02-06 11:42:45 +0000 | [diff] [blame] | 907 | Iop_ShlN8x8, Iop_ShlN16x4, Iop_ShlN32x2, |
sewardj | 2fdd416 | 2010-08-22 12:59:02 +0000 | [diff] [blame] | 908 | Iop_ShrN8x8, Iop_ShrN16x4, Iop_ShrN32x2, |
sewardj | d71ba83 | 2006-12-27 01:15:29 +0000 | [diff] [blame] | 909 | Iop_SarN8x8, Iop_SarN16x4, Iop_SarN32x2, |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 910 | |
sewardj | 2fdd416 | 2010-08-22 12:59:02 +0000 | [diff] [blame] | 911 | /* VECTOR x VECTOR SATURATING SHIFT */ |
| 912 | Iop_QShl8x8, Iop_QShl16x4, Iop_QShl32x2, Iop_QShl64x1, |
| 913 | Iop_QSal8x8, Iop_QSal16x4, Iop_QSal32x2, Iop_QSal64x1, |
| 914 | /* VECTOR x INTEGER SATURATING SHIFT */ |
| 915 | Iop_QShlN8Sx8, Iop_QShlN16Sx4, Iop_QShlN32Sx2, Iop_QShlN64Sx1, |
| 916 | Iop_QShlN8x8, Iop_QShlN16x4, Iop_QShlN32x2, Iop_QShlN64x1, |
| 917 | Iop_QSalN8x8, Iop_QSalN16x4, Iop_QSalN32x2, Iop_QSalN64x1, |
| 918 | |
sewardj | 5f438dd | 2011-06-16 11:36:23 +0000 | [diff] [blame] | 919 | /* NARROWING (binary) |
| 920 | -- narrow 2xI64 into 1xI64, hi half from left arg */ |
sewardj | c9bff7d | 2011-06-15 15:09:37 +0000 | [diff] [blame] | 921 | /* For saturated narrowing, I believe there are 4 variants of |
| 922 | the basic arithmetic operation, depending on the signedness |
| 923 | of argument and result. Here are examples that exemplify |
| 924 | what I mean: |
| 925 | |
| 926 | QNarrow16Uto8U ( UShort x ) if (x >u 255) x = 255; |
| 927 | return x[7:0]; |
| 928 | |
| 929 | QNarrow16Sto8S ( Short x ) if (x <s -128) x = -128; |
| 930 | if (x >s 127) x = 127; |
| 931 | return x[7:0]; |
| 932 | |
| 933 | QNarrow16Uto8S ( UShort x ) if (x >u 127) x = 127; |
| 934 | return x[7:0]; |
| 935 | |
| 936 | QNarrow16Sto8U ( Short x ) if (x <s 0) x = 0; |
| 937 | if (x >s 255) x = 255; |
| 938 | return x[7:0]; |
| 939 | */ |
sewardj | 5f438dd | 2011-06-16 11:36:23 +0000 | [diff] [blame] | 940 | Iop_QNarrowBin16Sto8Ux8, |
| 941 | Iop_QNarrowBin16Sto8Sx8, Iop_QNarrowBin32Sto16Sx4, |
sewardj | ad2c9ea | 2011-10-22 09:32:16 +0000 | [diff] [blame] | 942 | Iop_NarrowBin16to8x8, Iop_NarrowBin32to16x4, |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 943 | |
sewardj | 2fdd416 | 2010-08-22 12:59:02 +0000 | [diff] [blame] | 944 | /* INTERLEAVING */ |
| 945 | /* Interleave lanes from low or high halves of |
sewardj | 38a3f86 | 2005-01-13 15:06:51 +0000 | [diff] [blame] | 946 | operands. Most-significant result lane is from the left |
| 947 | arg. */ |
| 948 | Iop_InterleaveHI8x8, Iop_InterleaveHI16x4, Iop_InterleaveHI32x2, |
| 949 | Iop_InterleaveLO8x8, Iop_InterleaveLO16x4, Iop_InterleaveLO32x2, |
sewardj | 2fdd416 | 2010-08-22 12:59:02 +0000 | [diff] [blame] | 950 | /* Interleave odd/even lanes of operands. Most-significant result lane |
| 951 | is from the left arg. Note that Interleave{Odd,Even}Lanes32x2 are |
| 952 | identical to Interleave{HI,LO}32x2 and so are omitted.*/ |
| 953 | Iop_InterleaveOddLanes8x8, Iop_InterleaveEvenLanes8x8, |
| 954 | Iop_InterleaveOddLanes16x4, Iop_InterleaveEvenLanes16x4, |
| 955 | |
sewardj | d166e28 | 2008-02-06 11:42:45 +0000 | [diff] [blame] | 956 | /* CONCATENATION -- build a new value by concatenating either |
| 957 | the even or odd lanes of both operands. Note that |
| 958 | Cat{Odd,Even}Lanes32x2 are identical to Interleave{HI,LO}32x2 |
| 959 | and so are omitted. */ |
sewardj | 2fdd416 | 2010-08-22 12:59:02 +0000 | [diff] [blame] | 960 | Iop_CatOddLanes8x8, Iop_CatOddLanes16x4, |
| 961 | Iop_CatEvenLanes8x8, Iop_CatEvenLanes16x4, |
| 962 | |
| 963 | /* GET / SET elements of VECTOR |
| 964 | GET is binop (I64, I8) -> I<elem_size> |
| 965 | SET is triop (I64, I8, I<elem_size>) -> I64 */ |
| 966 | /* Note: the arm back-end handles only constant second argument */ |
| 967 | Iop_GetElem8x8, Iop_GetElem16x4, Iop_GetElem32x2, |
| 968 | Iop_SetElem8x8, Iop_SetElem16x4, Iop_SetElem32x2, |
| 969 | |
| 970 | /* DUPLICATING -- copy value to all lanes */ |
| 971 | Iop_Dup8x8, Iop_Dup16x4, Iop_Dup32x2, |
| 972 | |
| 973 | /* EXTRACT -- copy 8-arg3 highest bytes from arg1 to 8-arg3 lowest bytes |
| 974 | of result and arg3 lowest bytes of arg2 to arg3 highest bytes of |
| 975 | result. |
| 976 | It is a triop: (I64, I64, I8) -> I64 */ |
| 977 | /* Note: the arm back-end handles only constant third argumnet. */ |
| 978 | Iop_Extract64, |
| 979 | |
| 980 | /* REVERSE the order of elements in each Half-words, Words, |
| 981 | Double-words */ |
| 982 | /* Examples: |
| 983 | Reverse16_8x8([a,b,c,d,e,f,g,h]) = [b,a,d,c,f,e,h,g] |
| 984 | Reverse32_8x8([a,b,c,d,e,f,g,h]) = [d,c,b,a,h,g,f,e] |
| 985 | Reverse64_8x8([a,b,c,d,e,f,g,h]) = [h,g,f,e,d,c,b,a] */ |
| 986 | Iop_Reverse16_8x8, |
| 987 | Iop_Reverse32_8x8, Iop_Reverse32_16x4, |
| 988 | Iop_Reverse64_8x8, Iop_Reverse64_16x4, Iop_Reverse64_32x2, |
sewardj | d166e28 | 2008-02-06 11:42:45 +0000 | [diff] [blame] | 989 | |
| 990 | /* PERMUTING -- copy src bytes to dst, |
| 991 | as indexed by control vector bytes: |
| 992 | for i in 0 .. 7 . result[i] = argL[ argR[i] ] |
| 993 | argR[i] values may only be in the range 0 .. 7, else behaviour |
| 994 | is undefined. */ |
| 995 | Iop_Perm8x8, |
| 996 | |
sewardj | e13074c | 2012-11-08 10:57:08 +0000 | [diff] [blame] | 997 | /* MISC CONVERSION -- get high bits of each byte lane, a la |
| 998 | x86/amd64 pmovmskb */ |
| 999 | Iop_GetMSBs8x8, /* I64 -> I8 */ |
| 1000 | |
sewardj | 2fdd416 | 2010-08-22 12:59:02 +0000 | [diff] [blame] | 1001 | /* Vector Reciprocal Estimate and Vector Reciprocal Square Root Estimate |
| 1002 | See floating-point equiwalents for details. */ |
| 1003 | Iop_Recip32x2, Iop_Rsqrte32x2, |
| 1004 | |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 1005 | /* ------------------ Decimal Floating Point ------------------ */ |
| 1006 | |
| 1007 | /* ARITHMETIC INSTRUCTIONS 64-bit |
| 1008 | ---------------------------------- |
florian | 79e5a48 | 2013-06-06 19:12:46 +0000 | [diff] [blame] | 1009 | IRRoundingMode(I32) X D64 X D64 -> D64 |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 1010 | */ |
| 1011 | Iop_AddD64, Iop_SubD64, Iop_MulD64, Iop_DivD64, |
| 1012 | |
| 1013 | /* ARITHMETIC INSTRUCTIONS 128-bit |
| 1014 | ---------------------------------- |
florian | 79e5a48 | 2013-06-06 19:12:46 +0000 | [diff] [blame] | 1015 | IRRoundingMode(I32) X D128 X D128 -> D128 |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 1016 | */ |
| 1017 | Iop_AddD128, Iop_SubD128, Iop_MulD128, Iop_DivD128, |
| 1018 | |
sewardj | 26217b0 | 2012-04-12 17:19:48 +0000 | [diff] [blame] | 1019 | /* SHIFT SIGNIFICAND INSTRUCTIONS |
| 1020 | * The DFP significand is shifted by the number of digits specified |
| 1021 | * by the U8 operand. Digits shifted out of the leftmost digit are |
| 1022 | * lost. Zeros are supplied to the vacated positions on the right. |
| 1023 | * The sign of the result is the same as the sign of the original |
| 1024 | * operand. |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 1025 | * |
| 1026 | * D64 x U8 -> D64 left shift and right shift respectively */ |
sewardj | 26217b0 | 2012-04-12 17:19:48 +0000 | [diff] [blame] | 1027 | Iop_ShlD64, Iop_ShrD64, |
| 1028 | |
| 1029 | /* D128 x U8 -> D128 left shift and right shift respectively */ |
| 1030 | Iop_ShlD128, Iop_ShrD128, |
| 1031 | |
| 1032 | |
| 1033 | /* FORMAT CONVERSION INSTRUCTIONS |
| 1034 | * D32 -> D64 |
| 1035 | */ |
| 1036 | Iop_D32toD64, |
| 1037 | |
| 1038 | /* D64 -> D128 */ |
| 1039 | Iop_D64toD128, |
| 1040 | |
florian | b17e16f | 2013-01-12 22:02:07 +0000 | [diff] [blame] | 1041 | /* I32S -> D128 */ |
| 1042 | Iop_I32StoD128, |
| 1043 | |
| 1044 | /* I32U -> D128 */ |
| 1045 | Iop_I32UtoD128, |
| 1046 | |
sewardj | 26217b0 | 2012-04-12 17:19:48 +0000 | [diff] [blame] | 1047 | /* I64S -> D128 */ |
| 1048 | Iop_I64StoD128, |
| 1049 | |
florian | b17e16f | 2013-01-12 22:02:07 +0000 | [diff] [blame] | 1050 | /* I64U -> D128 */ |
| 1051 | Iop_I64UtoD128, |
| 1052 | |
florian | 79e5a48 | 2013-06-06 19:12:46 +0000 | [diff] [blame] | 1053 | /* IRRoundingMode(I32) x D64 -> D32 */ |
sewardj | 26217b0 | 2012-04-12 17:19:48 +0000 | [diff] [blame] | 1054 | Iop_D64toD32, |
| 1055 | |
florian | 79e5a48 | 2013-06-06 19:12:46 +0000 | [diff] [blame] | 1056 | /* IRRoundingMode(I32) x D128 -> D64 */ |
sewardj | 26217b0 | 2012-04-12 17:19:48 +0000 | [diff] [blame] | 1057 | Iop_D128toD64, |
| 1058 | |
florian | b17e16f | 2013-01-12 22:02:07 +0000 | [diff] [blame] | 1059 | /* I32S -> D64 */ |
| 1060 | Iop_I32StoD64, |
| 1061 | |
| 1062 | /* I32U -> D64 */ |
| 1063 | Iop_I32UtoD64, |
| 1064 | |
florian | 79e5a48 | 2013-06-06 19:12:46 +0000 | [diff] [blame] | 1065 | /* IRRoundingMode(I32) x I64 -> D64 */ |
sewardj | 26217b0 | 2012-04-12 17:19:48 +0000 | [diff] [blame] | 1066 | Iop_I64StoD64, |
| 1067 | |
florian | 79e5a48 | 2013-06-06 19:12:46 +0000 | [diff] [blame] | 1068 | /* IRRoundingMode(I32) x I64 -> D64 */ |
florian | b17e16f | 2013-01-12 22:02:07 +0000 | [diff] [blame] | 1069 | Iop_I64UtoD64, |
| 1070 | |
florian | 79e5a48 | 2013-06-06 19:12:46 +0000 | [diff] [blame] | 1071 | /* IRRoundingMode(I32) x D64 -> I32 */ |
florian | b17e16f | 2013-01-12 22:02:07 +0000 | [diff] [blame] | 1072 | Iop_D64toI32S, |
| 1073 | |
florian | 79e5a48 | 2013-06-06 19:12:46 +0000 | [diff] [blame] | 1074 | /* IRRoundingMode(I32) x D64 -> I32 */ |
florian | b17e16f | 2013-01-12 22:02:07 +0000 | [diff] [blame] | 1075 | Iop_D64toI32U, |
| 1076 | |
florian | 79e5a48 | 2013-06-06 19:12:46 +0000 | [diff] [blame] | 1077 | /* IRRoundingMode(I32) x D64 -> I64 */ |
sewardj | 26217b0 | 2012-04-12 17:19:48 +0000 | [diff] [blame] | 1078 | Iop_D64toI64S, |
| 1079 | |
florian | 79e5a48 | 2013-06-06 19:12:46 +0000 | [diff] [blame] | 1080 | /* IRRoundingMode(I32) x D64 -> I64 */ |
florian | b17e16f | 2013-01-12 22:02:07 +0000 | [diff] [blame] | 1081 | Iop_D64toI64U, |
| 1082 | |
florian | 79e5a48 | 2013-06-06 19:12:46 +0000 | [diff] [blame] | 1083 | /* IRRoundingMode(I32) x D128 -> I32 */ |
florian | b17e16f | 2013-01-12 22:02:07 +0000 | [diff] [blame] | 1084 | Iop_D128toI32S, |
| 1085 | |
florian | 79e5a48 | 2013-06-06 19:12:46 +0000 | [diff] [blame] | 1086 | /* IRRoundingMode(I32) x D128 -> I32 */ |
florian | b17e16f | 2013-01-12 22:02:07 +0000 | [diff] [blame] | 1087 | Iop_D128toI32U, |
| 1088 | |
florian | 79e5a48 | 2013-06-06 19:12:46 +0000 | [diff] [blame] | 1089 | /* IRRoundingMode(I32) x D128 -> I64 */ |
sewardj | 26217b0 | 2012-04-12 17:19:48 +0000 | [diff] [blame] | 1090 | Iop_D128toI64S, |
| 1091 | |
florian | 79e5a48 | 2013-06-06 19:12:46 +0000 | [diff] [blame] | 1092 | /* IRRoundingMode(I32) x D128 -> I64 */ |
florian | b17e16f | 2013-01-12 22:02:07 +0000 | [diff] [blame] | 1093 | Iop_D128toI64U, |
| 1094 | |
florian | b22838d | 2013-06-17 18:59:51 +0000 | [diff] [blame^] | 1095 | /* IRRoundingMode(I32) x F32 -> D32 */ |
| 1096 | Iop_F32toD32, |
| 1097 | |
| 1098 | /* IRRoundingMode(I32) x F32 -> D64 */ |
| 1099 | Iop_F32toD64, |
| 1100 | |
| 1101 | /* IRRoundingMode(I32) x F32 -> D128 */ |
| 1102 | Iop_F32toD128, |
| 1103 | |
| 1104 | /* IRRoundingMode(I32) x F64 -> D32 */ |
| 1105 | Iop_F64toD32, |
| 1106 | |
florian | 79e5a48 | 2013-06-06 19:12:46 +0000 | [diff] [blame] | 1107 | /* IRRoundingMode(I32) x F64 -> D64 */ |
florian | 37c57f3 | 2013-05-05 15:04:30 +0000 | [diff] [blame] | 1108 | Iop_F64toD64, |
| 1109 | |
florian | 79e5a48 | 2013-06-06 19:12:46 +0000 | [diff] [blame] | 1110 | /* IRRoundingMode(I32) x F64 -> D128 */ |
florian | 37c57f3 | 2013-05-05 15:04:30 +0000 | [diff] [blame] | 1111 | Iop_F64toD128, |
| 1112 | |
florian | b22838d | 2013-06-17 18:59:51 +0000 | [diff] [blame^] | 1113 | /* IRRoundingMode(I32) x F128 -> D32 */ |
| 1114 | Iop_F128toD32, |
| 1115 | |
| 1116 | /* IRRoundingMode(I32) x F128 -> D64 */ |
| 1117 | Iop_F128toD64, |
florian | 37c57f3 | 2013-05-05 15:04:30 +0000 | [diff] [blame] | 1118 | |
florian | 79e5a48 | 2013-06-06 19:12:46 +0000 | [diff] [blame] | 1119 | /* IRRoundingMode(I32) x F128 -> D128 */ |
florian | 37c57f3 | 2013-05-05 15:04:30 +0000 | [diff] [blame] | 1120 | Iop_F128toD128, |
| 1121 | |
florian | b22838d | 2013-06-17 18:59:51 +0000 | [diff] [blame^] | 1122 | /* IRRoundingMode(I32) x D32 -> F32 */ |
| 1123 | Iop_D32toF32, |
| 1124 | |
| 1125 | /* IRRoundingMode(I32) x D32 -> F64 */ |
| 1126 | Iop_D32toF64, |
| 1127 | |
| 1128 | /* IRRoundingMode(I32) x D32 -> F128 */ |
| 1129 | Iop_D32toF128, |
| 1130 | |
| 1131 | /* IRRoundingMode(I32) x D64 -> F32 */ |
| 1132 | Iop_D64toF32, |
| 1133 | |
| 1134 | /* IRRoundingMode(I32) x D64 -> F64 */ |
| 1135 | Iop_D64toF64, |
| 1136 | |
| 1137 | /* IRRoundingMode(I32) x D64 -> F128 */ |
| 1138 | Iop_D64toF128, |
| 1139 | |
| 1140 | /* IRRoundingMode(I32) x D128 -> F32 */ |
| 1141 | Iop_D128toF32, |
| 1142 | |
| 1143 | /* IRRoundingMode(I32) x D128 -> F64 */ |
| 1144 | Iop_D128toF64, |
| 1145 | |
florian | 79e5a48 | 2013-06-06 19:12:46 +0000 | [diff] [blame] | 1146 | /* IRRoundingMode(I32) x D128 -> F128 */ |
florian | 37c57f3 | 2013-05-05 15:04:30 +0000 | [diff] [blame] | 1147 | Iop_D128toF128, |
| 1148 | |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 1149 | /* ROUNDING INSTRUCTIONS |
| 1150 | * IRRoundingMode(I32) x D64 -> D64 |
carll | cea07cc | 2013-01-22 20:25:31 +0000 | [diff] [blame] | 1151 | * The D64 operand, if a finite number, it is rounded to a |
| 1152 | * floating point integer value, i.e. no fractional part. |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 1153 | */ |
| 1154 | Iop_RoundD64toInt, |
| 1155 | |
| 1156 | /* IRRoundingMode(I32) x D128 -> D128 */ |
| 1157 | Iop_RoundD128toInt, |
| 1158 | |
| 1159 | /* COMPARE INSTRUCTIONS |
| 1160 | * D64 x D64 -> IRCmpD64Result(I32) */ |
| 1161 | Iop_CmpD64, |
| 1162 | |
florian | daa4084 | 2012-12-21 20:24:24 +0000 | [diff] [blame] | 1163 | /* D128 x D128 -> IRCmpD128Result(I32) */ |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 1164 | Iop_CmpD128, |
| 1165 | |
florian | 20c6bca | 2012-12-26 17:47:19 +0000 | [diff] [blame] | 1166 | /* COMPARE BIASED EXPONENET INSTRUCTIONS |
| 1167 | * D64 x D64 -> IRCmpD64Result(I32) */ |
| 1168 | Iop_CmpExpD64, |
| 1169 | |
| 1170 | /* D128 x D128 -> IRCmpD128Result(I32) */ |
| 1171 | Iop_CmpExpD128, |
| 1172 | |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 1173 | /* QUANTIZE AND ROUND INSTRUCTIONS |
| 1174 | * The source operand is converted and rounded to the form with the |
| 1175 | * immediate exponent specified by the rounding and exponent parameter. |
| 1176 | * |
| 1177 | * The second operand is converted and rounded to the form |
| 1178 | * of the first operand's exponent and the rounded based on the specified |
| 1179 | * rounding mode parameter. |
| 1180 | * |
florian | 79e5a48 | 2013-06-06 19:12:46 +0000 | [diff] [blame] | 1181 | * IRRoundingMode(I32) x D64 x D64-> D64 */ |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 1182 | Iop_QuantizeD64, |
| 1183 | |
florian | 79e5a48 | 2013-06-06 19:12:46 +0000 | [diff] [blame] | 1184 | /* IRRoundingMode(I32) x D128 x D128 -> D128 */ |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 1185 | Iop_QuantizeD128, |
| 1186 | |
florian | 79e5a48 | 2013-06-06 19:12:46 +0000 | [diff] [blame] | 1187 | /* IRRoundingMode(I32) x I8 x D64 -> D64 |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 1188 | * The Decimal Floating point operand is rounded to the requested |
| 1189 | * significance given by the I8 operand as specified by the rounding |
| 1190 | * mode. |
| 1191 | */ |
| 1192 | Iop_SignificanceRoundD64, |
| 1193 | |
florian | 79e5a48 | 2013-06-06 19:12:46 +0000 | [diff] [blame] | 1194 | /* IRRoundingMode(I32) x I8 x D128 -> D128 */ |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 1195 | Iop_SignificanceRoundD128, |
| 1196 | |
| 1197 | /* EXTRACT AND INSERT INSTRUCTIONS |
| 1198 | * D64 -> I64 |
| 1199 | * The exponent of the D32 or D64 operand is extracted. The |
| 1200 | * extracted exponent is converted to a 64-bit signed binary integer. |
| 1201 | */ |
| 1202 | Iop_ExtractExpD64, |
| 1203 | |
| 1204 | /* D128 -> I64 */ |
| 1205 | Iop_ExtractExpD128, |
| 1206 | |
florian | 4bbd3ec | 2012-12-27 20:01:13 +0000 | [diff] [blame] | 1207 | /* D64 -> I64 |
| 1208 | * The number of significand digits of the D64 operand is extracted. |
| 1209 | * The number is stored as a 64-bit signed binary integer. |
| 1210 | */ |
| 1211 | Iop_ExtractSigD64, |
| 1212 | |
| 1213 | /* D128 -> I64 */ |
| 1214 | Iop_ExtractSigD128, |
| 1215 | |
carll | cea07cc | 2013-01-22 20:25:31 +0000 | [diff] [blame] | 1216 | /* I64 x D64 -> D64 |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 1217 | * The exponent is specified by the first I64 operand the signed |
| 1218 | * significand is given by the second I64 value. The result is a D64 |
| 1219 | * value consisting of the specified significand and exponent whose |
| 1220 | * sign is that of the specified significand. |
| 1221 | */ |
| 1222 | Iop_InsertExpD64, |
| 1223 | |
carll | cea07cc | 2013-01-22 20:25:31 +0000 | [diff] [blame] | 1224 | /* I64 x D128 -> D128 */ |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 1225 | Iop_InsertExpD128, |
| 1226 | |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 1227 | /* Support for 128-bit DFP type */ |
| 1228 | Iop_D64HLtoD128, Iop_D128HItoD64, Iop_D128LOtoD64, |
| 1229 | |
sewardj | 4c96e61 | 2012-06-02 23:47:02 +0000 | [diff] [blame] | 1230 | /* I64 -> I64 |
| 1231 | * Convert 50-bit densely packed BCD string to 60 bit BCD string |
| 1232 | */ |
| 1233 | Iop_DPBtoBCD, |
| 1234 | |
| 1235 | /* I64 -> I64 |
| 1236 | * Convert 60 bit BCD string to 50-bit densely packed BCD string |
| 1237 | */ |
| 1238 | Iop_BCDtoDPB, |
| 1239 | |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 1240 | /* Conversion I64 -> D64 */ |
| 1241 | Iop_ReinterpI64asD64, |
| 1242 | |
sewardj | 5eff1c5 | 2012-04-29 20:19:17 +0000 | [diff] [blame] | 1243 | /* Conversion D64 -> I64 */ |
| 1244 | Iop_ReinterpD64asI64, |
| 1245 | |
sewardj | 164f927 | 2004-12-09 00:39:32 +0000 | [diff] [blame] | 1246 | /* ------------------ 128-bit SIMD FP. ------------------ */ |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 1247 | |
| 1248 | /* --- 32x4 vector FP --- */ |
| 1249 | |
| 1250 | /* binary */ |
| 1251 | Iop_Add32Fx4, Iop_Sub32Fx4, Iop_Mul32Fx4, Iop_Div32Fx4, |
| 1252 | Iop_Max32Fx4, Iop_Min32Fx4, |
sewardj | 2fdd416 | 2010-08-22 12:59:02 +0000 | [diff] [blame] | 1253 | Iop_Add32Fx2, Iop_Sub32Fx2, |
| 1254 | /* Note: For the following compares, the ppc and arm front-ends assume a |
cerion | f294eb3 | 2005-11-16 17:21:10 +0000 | [diff] [blame] | 1255 | nan in a lane of either argument returns zero for that lane. */ |
sewardj | 2fdd416 | 2010-08-22 12:59:02 +0000 | [diff] [blame] | 1256 | Iop_CmpEQ32Fx4, Iop_CmpLT32Fx4, Iop_CmpLE32Fx4, Iop_CmpUN32Fx4, |
cerion | 206c364 | 2005-11-14 00:35:59 +0000 | [diff] [blame] | 1257 | Iop_CmpGT32Fx4, Iop_CmpGE32Fx4, |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 1258 | |
sewardj | 2fdd416 | 2010-08-22 12:59:02 +0000 | [diff] [blame] | 1259 | /* Vector Absolute */ |
| 1260 | Iop_Abs32Fx4, |
| 1261 | |
| 1262 | /* Pairwise Max and Min. See integer pairwise operations for details. */ |
| 1263 | Iop_PwMax32Fx4, Iop_PwMin32Fx4, |
| 1264 | |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 1265 | /* unary */ |
sewardj | 2fdd416 | 2010-08-22 12:59:02 +0000 | [diff] [blame] | 1266 | Iop_Sqrt32Fx4, Iop_RSqrt32Fx4, |
| 1267 | Iop_Neg32Fx4, |
| 1268 | |
| 1269 | /* Vector Reciprocal Estimate finds an approximate reciprocal of each |
| 1270 | element in the operand vector, and places the results in the destination |
| 1271 | vector. */ |
| 1272 | Iop_Recip32Fx4, |
| 1273 | |
| 1274 | /* Vector Reciprocal Step computes (2.0 - arg1 * arg2). |
| 1275 | Note, that if one of the arguments is zero and another one is infinity |
| 1276 | of arbitrary sign the result of the operation is 2.0. */ |
| 1277 | Iop_Recps32Fx4, |
| 1278 | |
| 1279 | /* Vector Reciprocal Square Root Estimate finds an approximate reciprocal |
| 1280 | square root of each element in the operand vector. */ |
| 1281 | Iop_Rsqrte32Fx4, |
| 1282 | |
| 1283 | /* Vector Reciprocal Square Root Step computes (3.0 - arg1 * arg2) / 2.0. |
| 1284 | Note, that of one of the arguments is zero and another one is infiinty |
| 1285 | of arbitrary sign the result of the operation is 1.5. */ |
| 1286 | Iop_Rsqrts32Fx4, |
| 1287 | |
cerion | f294eb3 | 2005-11-16 17:21:10 +0000 | [diff] [blame] | 1288 | /* --- Int to/from FP conversion --- */ |
| 1289 | /* Unlike the standard fp conversions, these irops take no |
| 1290 | rounding mode argument. Instead the irop trailers _R{M,P,N,Z} |
| 1291 | indicate the mode: {-inf, +inf, nearest, zero} respectively. */ |
sewardj | 2fdd416 | 2010-08-22 12:59:02 +0000 | [diff] [blame] | 1292 | Iop_I32UtoFx4, Iop_I32StoFx4, /* I32x4 -> F32x4 */ |
| 1293 | Iop_FtoI32Ux4_RZ, Iop_FtoI32Sx4_RZ, /* F32x4 -> I32x4 */ |
| 1294 | Iop_QFtoI32Ux4_RZ, Iop_QFtoI32Sx4_RZ, /* F32x4 -> I32x4 (with saturation) */ |
cerion | f294eb3 | 2005-11-16 17:21:10 +0000 | [diff] [blame] | 1295 | Iop_RoundF32x4_RM, Iop_RoundF32x4_RP, /* round to fp integer */ |
| 1296 | Iop_RoundF32x4_RN, Iop_RoundF32x4_RZ, /* round to fp integer */ |
sewardj | 2fdd416 | 2010-08-22 12:59:02 +0000 | [diff] [blame] | 1297 | /* Fixed32 format is floating-point number with fixed number of fraction |
| 1298 | bits. The number of fraction bits is passed as a second argument of |
| 1299 | type I8. */ |
| 1300 | Iop_F32ToFixed32Ux4_RZ, Iop_F32ToFixed32Sx4_RZ, /* fp -> fixed-point */ |
| 1301 | Iop_Fixed32UToF32x4_RN, Iop_Fixed32SToF32x4_RN, /* fixed-point -> fp */ |
| 1302 | |
| 1303 | /* --- Single to/from half conversion --- */ |
sewardj | 5f438dd | 2011-06-16 11:36:23 +0000 | [diff] [blame] | 1304 | /* FIXME: what kind of rounding in F32x4 -> F16x4 case? */ |
sewardj | 2fdd416 | 2010-08-22 12:59:02 +0000 | [diff] [blame] | 1305 | Iop_F32toF16x4, Iop_F16toF32x4, /* F32x4 <-> F16x4 */ |
cerion | f294eb3 | 2005-11-16 17:21:10 +0000 | [diff] [blame] | 1306 | |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 1307 | /* --- 32x4 lowest-lane-only scalar FP --- */ |
| 1308 | |
| 1309 | /* In binary cases, upper 3/4 is copied from first operand. In |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 1310 | unary cases, upper 3/4 is copied from the operand. */ |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 1311 | |
| 1312 | /* binary */ |
| 1313 | Iop_Add32F0x4, Iop_Sub32F0x4, Iop_Mul32F0x4, Iop_Div32F0x4, |
| 1314 | Iop_Max32F0x4, Iop_Min32F0x4, |
sewardj | 636ad76 | 2004-12-07 11:16:04 +0000 | [diff] [blame] | 1315 | Iop_CmpEQ32F0x4, Iop_CmpLT32F0x4, Iop_CmpLE32F0x4, Iop_CmpUN32F0x4, |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 1316 | |
| 1317 | /* unary */ |
| 1318 | Iop_Recip32F0x4, Iop_Sqrt32F0x4, Iop_RSqrt32F0x4, |
sewardj | 636ad76 | 2004-12-07 11:16:04 +0000 | [diff] [blame] | 1319 | |
| 1320 | /* --- 64x2 vector FP --- */ |
| 1321 | |
| 1322 | /* binary */ |
| 1323 | Iop_Add64Fx2, Iop_Sub64Fx2, Iop_Mul64Fx2, Iop_Div64Fx2, |
| 1324 | Iop_Max64Fx2, Iop_Min64Fx2, |
| 1325 | Iop_CmpEQ64Fx2, Iop_CmpLT64Fx2, Iop_CmpLE64Fx2, Iop_CmpUN64Fx2, |
| 1326 | |
| 1327 | /* unary */ |
| 1328 | Iop_Recip64Fx2, Iop_Sqrt64Fx2, Iop_RSqrt64Fx2, |
| 1329 | |
| 1330 | /* --- 64x2 lowest-lane-only scalar FP --- */ |
| 1331 | |
| 1332 | /* In binary cases, upper half is copied from first operand. In |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 1333 | unary cases, upper half is copied from the operand. */ |
sewardj | 636ad76 | 2004-12-07 11:16:04 +0000 | [diff] [blame] | 1334 | |
| 1335 | /* binary */ |
| 1336 | Iop_Add64F0x2, Iop_Sub64F0x2, Iop_Mul64F0x2, Iop_Div64F0x2, |
| 1337 | Iop_Max64F0x2, Iop_Min64F0x2, |
| 1338 | Iop_CmpEQ64F0x2, Iop_CmpLT64F0x2, Iop_CmpLE64F0x2, Iop_CmpUN64F0x2, |
| 1339 | |
| 1340 | /* unary */ |
| 1341 | Iop_Recip64F0x2, Iop_Sqrt64F0x2, Iop_RSqrt64F0x2, |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 1342 | |
| 1343 | /* --- pack / unpack --- */ |
| 1344 | |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 1345 | /* 64 <-> 128 bit vector */ |
| 1346 | Iop_V128to64, // :: V128 -> I64, low half |
| 1347 | Iop_V128HIto64, // :: V128 -> I64, high half |
| 1348 | Iop_64HLtoV128, // :: (I64,I64) -> V128 |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 1349 | |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 1350 | Iop_64UtoV128, |
| 1351 | Iop_SetV128lo64, |
sewardj | 164f927 | 2004-12-09 00:39:32 +0000 | [diff] [blame] | 1352 | |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 1353 | /* 32 <-> 128 bit vector */ |
| 1354 | Iop_32UtoV128, |
| 1355 | Iop_V128to32, // :: V128 -> I32, lowest lane |
| 1356 | Iop_SetV128lo32, // :: (V128,I32) -> V128 |
sewardj | 70f676d | 2004-12-10 14:59:57 +0000 | [diff] [blame] | 1357 | |
sewardj | 164f927 | 2004-12-09 00:39:32 +0000 | [diff] [blame] | 1358 | /* ------------------ 128-bit SIMD Integer. ------------------ */ |
| 1359 | |
| 1360 | /* BITWISE OPS */ |
sewardj | f0c1c58 | 2005-02-07 23:47:38 +0000 | [diff] [blame] | 1361 | Iop_NotV128, |
| 1362 | Iop_AndV128, Iop_OrV128, Iop_XorV128, |
sewardj | 164f927 | 2004-12-09 00:39:32 +0000 | [diff] [blame] | 1363 | |
cerion | f887b3e | 2005-09-13 16:34:28 +0000 | [diff] [blame] | 1364 | /* VECTOR SHIFT (shift amt :: Ity_I8) */ |
| 1365 | Iop_ShlV128, Iop_ShrV128, |
| 1366 | |
sewardj | 2e38386 | 2004-12-12 16:46:47 +0000 | [diff] [blame] | 1367 | /* MISC (vector integer cmp != 0) */ |
| 1368 | Iop_CmpNEZ8x16, Iop_CmpNEZ16x8, Iop_CmpNEZ32x4, Iop_CmpNEZ64x2, |
sewardj | 70f676d | 2004-12-10 14:59:57 +0000 | [diff] [blame] | 1369 | |
sewardj | 164f927 | 2004-12-09 00:39:32 +0000 | [diff] [blame] | 1370 | /* ADDITION (normal / unsigned sat / signed sat) */ |
sewardj | 2fdd416 | 2010-08-22 12:59:02 +0000 | [diff] [blame] | 1371 | Iop_Add8x16, Iop_Add16x8, Iop_Add32x4, Iop_Add64x2, |
| 1372 | Iop_QAdd8Ux16, Iop_QAdd16Ux8, Iop_QAdd32Ux4, Iop_QAdd64Ux2, |
| 1373 | Iop_QAdd8Sx16, Iop_QAdd16Sx8, Iop_QAdd32Sx4, Iop_QAdd64Sx2, |
sewardj | 164f927 | 2004-12-09 00:39:32 +0000 | [diff] [blame] | 1374 | |
| 1375 | /* SUBTRACTION (normal / unsigned sat / signed sat) */ |
sewardj | 2fdd416 | 2010-08-22 12:59:02 +0000 | [diff] [blame] | 1376 | Iop_Sub8x16, Iop_Sub16x8, Iop_Sub32x4, Iop_Sub64x2, |
| 1377 | Iop_QSub8Ux16, Iop_QSub16Ux8, Iop_QSub32Ux4, Iop_QSub64Ux2, |
| 1378 | Iop_QSub8Sx16, Iop_QSub16Sx8, Iop_QSub32Sx4, Iop_QSub64Sx2, |
sewardj | 164f927 | 2004-12-09 00:39:32 +0000 | [diff] [blame] | 1379 | |
| 1380 | /* MULTIPLICATION (normal / high half of signed/unsigned) */ |
sewardj | 2fdd416 | 2010-08-22 12:59:02 +0000 | [diff] [blame] | 1381 | Iop_Mul8x16, Iop_Mul16x8, Iop_Mul32x4, |
| 1382 | Iop_MulHi16Ux8, Iop_MulHi32Ux4, |
| 1383 | Iop_MulHi16Sx8, Iop_MulHi32Sx4, |
cerion | 24d06f1 | 2005-11-09 21:34:20 +0000 | [diff] [blame] | 1384 | /* (widening signed/unsigned of even lanes, with lowest lane=zero) */ |
cerion | 1ac656a | 2005-11-04 19:44:48 +0000 | [diff] [blame] | 1385 | Iop_MullEven8Ux16, Iop_MullEven16Ux8, |
| 1386 | Iop_MullEven8Sx16, Iop_MullEven16Sx8, |
sewardj | 2fdd416 | 2010-08-22 12:59:02 +0000 | [diff] [blame] | 1387 | /* FIXME: document these */ |
| 1388 | Iop_Mull8Ux8, Iop_Mull8Sx8, |
| 1389 | Iop_Mull16Ux4, Iop_Mull16Sx4, |
| 1390 | Iop_Mull32Ux2, Iop_Mull32Sx2, |
| 1391 | /* Vector Saturating Doubling Multiply Returning High Half and |
| 1392 | Vector Saturating Rounding Doubling Multiply Returning High Half */ |
| 1393 | /* These IROp's multiply corresponding elements in two vectors, double |
| 1394 | the results, and place the most significant half of the final results |
| 1395 | in the destination vector. The results are truncated or rounded. If |
| 1396 | any of the results overflow, they are saturated. */ |
| 1397 | Iop_QDMulHi16Sx8, Iop_QDMulHi32Sx4, |
| 1398 | Iop_QRDMulHi16Sx8, Iop_QRDMulHi32Sx4, |
| 1399 | /* Doubling saturating multiplication (long) (I64, I64) -> V128 */ |
| 1400 | Iop_QDMulLong16Sx4, Iop_QDMulLong32Sx2, |
| 1401 | /* Plynomial multiplication treats it's arguments as coefficients of |
| 1402 | polynoms over {0, 1}. */ |
| 1403 | Iop_PolynomialMul8x16, /* (V128, V128) -> V128 */ |
| 1404 | Iop_PolynomialMull8x8, /* (I64, I64) -> V128 */ |
| 1405 | |
| 1406 | /* PAIRWISE operations */ |
| 1407 | /* Iop_PwFoo16x4( [a,b,c,d], [e,f,g,h] ) = |
| 1408 | [Foo16(a,b), Foo16(c,d), Foo16(e,f), Foo16(g,h)] */ |
| 1409 | Iop_PwAdd8x16, Iop_PwAdd16x8, Iop_PwAdd32x4, |
| 1410 | Iop_PwAdd32Fx2, |
| 1411 | /* Longening variant is unary. The resulting vector contains two times |
| 1412 | less elements than operand, but they are two times wider. |
| 1413 | Example: |
| 1414 | Iop_PwAddL16Ux4( [a,b,c,d] ) = [a+b,c+d] |
| 1415 | where a+b and c+d are unsigned 32-bit values. */ |
| 1416 | Iop_PwAddL8Ux16, Iop_PwAddL16Ux8, Iop_PwAddL32Ux4, |
| 1417 | Iop_PwAddL8Sx16, Iop_PwAddL16Sx8, Iop_PwAddL32Sx4, |
| 1418 | |
| 1419 | /* ABSOLUTE VALUE */ |
| 1420 | Iop_Abs8x16, Iop_Abs16x8, Iop_Abs32x4, |
cerion | 1ac656a | 2005-11-04 19:44:48 +0000 | [diff] [blame] | 1421 | |
sewardj | 5ce5fd6 | 2005-04-19 23:06:11 +0000 | [diff] [blame] | 1422 | /* AVERAGING: note: (arg1 + arg2 + 1) >>u 1 */ |
cerion | f887b3e | 2005-09-13 16:34:28 +0000 | [diff] [blame] | 1423 | Iop_Avg8Ux16, Iop_Avg16Ux8, Iop_Avg32Ux4, |
| 1424 | Iop_Avg8Sx16, Iop_Avg16Sx8, Iop_Avg32Sx4, |
sewardj | 164f927 | 2004-12-09 00:39:32 +0000 | [diff] [blame] | 1425 | |
| 1426 | /* MIN/MAX */ |
cerion | f887b3e | 2005-09-13 16:34:28 +0000 | [diff] [blame] | 1427 | Iop_Max8Sx16, Iop_Max16Sx8, Iop_Max32Sx4, |
| 1428 | Iop_Max8Ux16, Iop_Max16Ux8, Iop_Max32Ux4, |
| 1429 | Iop_Min8Sx16, Iop_Min16Sx8, Iop_Min32Sx4, |
| 1430 | Iop_Min8Ux16, Iop_Min16Ux8, Iop_Min32Ux4, |
sewardj | 164f927 | 2004-12-09 00:39:32 +0000 | [diff] [blame] | 1431 | |
| 1432 | /* COMPARISON */ |
sewardj | d881562 | 2011-10-19 15:24:01 +0000 | [diff] [blame] | 1433 | Iop_CmpEQ8x16, Iop_CmpEQ16x8, Iop_CmpEQ32x4, Iop_CmpEQ64x2, |
sewardj | 69d98e3 | 2010-06-18 08:17:41 +0000 | [diff] [blame] | 1434 | Iop_CmpGT8Sx16, Iop_CmpGT16Sx8, Iop_CmpGT32Sx4, Iop_CmpGT64Sx2, |
cerion | f887b3e | 2005-09-13 16:34:28 +0000 | [diff] [blame] | 1435 | Iop_CmpGT8Ux16, Iop_CmpGT16Ux8, Iop_CmpGT32Ux4, |
sewardj | 164f927 | 2004-12-09 00:39:32 +0000 | [diff] [blame] | 1436 | |
sewardj | 2fdd416 | 2010-08-22 12:59:02 +0000 | [diff] [blame] | 1437 | /* COUNT ones / leading zeroes / leading sign bits (not including topmost |
| 1438 | bit) */ |
| 1439 | Iop_Cnt8x16, |
| 1440 | Iop_Clz8Sx16, Iop_Clz16Sx8, Iop_Clz32Sx4, |
| 1441 | Iop_Cls8Sx16, Iop_Cls16Sx8, Iop_Cls32Sx4, |
| 1442 | |
sewardj | 164f927 | 2004-12-09 00:39:32 +0000 | [diff] [blame] | 1443 | /* VECTOR x SCALAR SHIFT (shift amt :: Ity_I8) */ |
cerion | 2a4b845 | 2005-09-15 16:28:36 +0000 | [diff] [blame] | 1444 | Iop_ShlN8x16, Iop_ShlN16x8, Iop_ShlN32x4, Iop_ShlN64x2, |
| 1445 | Iop_ShrN8x16, Iop_ShrN16x8, Iop_ShrN32x4, Iop_ShrN64x2, |
sewardj | 2fdd416 | 2010-08-22 12:59:02 +0000 | [diff] [blame] | 1446 | Iop_SarN8x16, Iop_SarN16x8, Iop_SarN32x4, Iop_SarN64x2, |
sewardj | 164f927 | 2004-12-09 00:39:32 +0000 | [diff] [blame] | 1447 | |
cerion | f887b3e | 2005-09-13 16:34:28 +0000 | [diff] [blame] | 1448 | /* VECTOR x VECTOR SHIFT / ROTATE */ |
sewardj | 2fdd416 | 2010-08-22 12:59:02 +0000 | [diff] [blame] | 1449 | Iop_Shl8x16, Iop_Shl16x8, Iop_Shl32x4, Iop_Shl64x2, |
| 1450 | Iop_Shr8x16, Iop_Shr16x8, Iop_Shr32x4, Iop_Shr64x2, |
| 1451 | Iop_Sar8x16, Iop_Sar16x8, Iop_Sar32x4, Iop_Sar64x2, |
| 1452 | Iop_Sal8x16, Iop_Sal16x8, Iop_Sal32x4, Iop_Sal64x2, |
sewardj | 1bee561 | 2005-11-10 18:10:58 +0000 | [diff] [blame] | 1453 | Iop_Rol8x16, Iop_Rol16x8, Iop_Rol32x4, |
cerion | f887b3e | 2005-09-13 16:34:28 +0000 | [diff] [blame] | 1454 | |
sewardj | 2fdd416 | 2010-08-22 12:59:02 +0000 | [diff] [blame] | 1455 | /* VECTOR x VECTOR SATURATING SHIFT */ |
| 1456 | Iop_QShl8x16, Iop_QShl16x8, Iop_QShl32x4, Iop_QShl64x2, |
| 1457 | Iop_QSal8x16, Iop_QSal16x8, Iop_QSal32x4, Iop_QSal64x2, |
| 1458 | /* VECTOR x INTEGER SATURATING SHIFT */ |
| 1459 | Iop_QShlN8Sx16, Iop_QShlN16Sx8, Iop_QShlN32Sx4, Iop_QShlN64Sx2, |
| 1460 | Iop_QShlN8x16, Iop_QShlN16x8, Iop_QShlN32x4, Iop_QShlN64x2, |
| 1461 | Iop_QSalN8x16, Iop_QSalN16x8, Iop_QSalN32x4, Iop_QSalN64x2, |
| 1462 | |
sewardj | 5f438dd | 2011-06-16 11:36:23 +0000 | [diff] [blame] | 1463 | /* NARROWING (binary) |
| 1464 | -- narrow 2xV128 into 1xV128, hi half from left arg */ |
sewardj | c9bff7d | 2011-06-15 15:09:37 +0000 | [diff] [blame] | 1465 | /* See comments above w.r.t. U vs S issues in saturated narrowing. */ |
sewardj | 5f438dd | 2011-06-16 11:36:23 +0000 | [diff] [blame] | 1466 | Iop_QNarrowBin16Sto8Ux16, Iop_QNarrowBin32Sto16Ux8, |
| 1467 | Iop_QNarrowBin16Sto8Sx16, Iop_QNarrowBin32Sto16Sx8, |
| 1468 | Iop_QNarrowBin16Uto8Ux16, Iop_QNarrowBin32Uto16Ux8, |
| 1469 | Iop_NarrowBin16to8x16, Iop_NarrowBin32to16x8, |
sewardj | 164f927 | 2004-12-09 00:39:32 +0000 | [diff] [blame] | 1470 | |
sewardj | 5f438dd | 2011-06-16 11:36:23 +0000 | [diff] [blame] | 1471 | /* NARROWING (unary) -- narrow V128 into I64 */ |
| 1472 | Iop_NarrowUn16to8x8, Iop_NarrowUn32to16x4, Iop_NarrowUn64to32x2, |
| 1473 | /* Saturating narrowing from signed source to signed/unsigned destination */ |
| 1474 | Iop_QNarrowUn16Sto8Sx8, Iop_QNarrowUn32Sto16Sx4, Iop_QNarrowUn64Sto32Sx2, |
| 1475 | Iop_QNarrowUn16Sto8Ux8, Iop_QNarrowUn32Sto16Ux4, Iop_QNarrowUn64Sto32Ux2, |
| 1476 | /* Saturating narrowing from unsigned source to unsigned destination */ |
| 1477 | Iop_QNarrowUn16Uto8Ux8, Iop_QNarrowUn32Uto16Ux4, Iop_QNarrowUn64Uto32Ux2, |
| 1478 | |
| 1479 | /* WIDENING -- sign or zero extend each element of the argument |
| 1480 | vector to the twice original size. The resulting vector consists of |
sewardj | 2fdd416 | 2010-08-22 12:59:02 +0000 | [diff] [blame] | 1481 | the same number of elements but each element and the vector itself |
sewardj | 5f438dd | 2011-06-16 11:36:23 +0000 | [diff] [blame] | 1482 | are twice as wide. |
sewardj | 2fdd416 | 2010-08-22 12:59:02 +0000 | [diff] [blame] | 1483 | All operations are I64->V128. |
| 1484 | Example |
sewardj | 5f438dd | 2011-06-16 11:36:23 +0000 | [diff] [blame] | 1485 | Iop_Widen32Sto64x2( [a, b] ) = [c, d] |
sewardj | 2fdd416 | 2010-08-22 12:59:02 +0000 | [diff] [blame] | 1486 | where c = Iop_32Sto64(a) and d = Iop_32Sto64(b) */ |
sewardj | 5f438dd | 2011-06-16 11:36:23 +0000 | [diff] [blame] | 1487 | Iop_Widen8Uto16x8, Iop_Widen16Uto32x4, Iop_Widen32Uto64x2, |
| 1488 | Iop_Widen8Sto16x8, Iop_Widen16Sto32x4, Iop_Widen32Sto64x2, |
sewardj | 2fdd416 | 2010-08-22 12:59:02 +0000 | [diff] [blame] | 1489 | |
| 1490 | /* INTERLEAVING */ |
| 1491 | /* Interleave lanes from low or high halves of |
sewardj | 164f927 | 2004-12-09 00:39:32 +0000 | [diff] [blame] | 1492 | operands. Most-significant result lane is from the left |
| 1493 | arg. */ |
| 1494 | Iop_InterleaveHI8x16, Iop_InterleaveHI16x8, |
| 1495 | Iop_InterleaveHI32x4, Iop_InterleaveHI64x2, |
sewardj | 2fdd416 | 2010-08-22 12:59:02 +0000 | [diff] [blame] | 1496 | Iop_InterleaveLO8x16, Iop_InterleaveLO16x8, |
cerion | f887b3e | 2005-09-13 16:34:28 +0000 | [diff] [blame] | 1497 | Iop_InterleaveLO32x4, Iop_InterleaveLO64x2, |
sewardj | 2fdd416 | 2010-08-22 12:59:02 +0000 | [diff] [blame] | 1498 | /* Interleave odd/even lanes of operands. Most-significant result lane |
| 1499 | is from the left arg. */ |
| 1500 | Iop_InterleaveOddLanes8x16, Iop_InterleaveEvenLanes8x16, |
| 1501 | Iop_InterleaveOddLanes16x8, Iop_InterleaveEvenLanes16x8, |
| 1502 | Iop_InterleaveOddLanes32x4, Iop_InterleaveEvenLanes32x4, |
| 1503 | |
| 1504 | /* CONCATENATION -- build a new value by concatenating either |
| 1505 | the even or odd lanes of both operands. */ |
| 1506 | Iop_CatOddLanes8x16, Iop_CatOddLanes16x8, Iop_CatOddLanes32x4, |
| 1507 | Iop_CatEvenLanes8x16, Iop_CatEvenLanes16x8, Iop_CatEvenLanes32x4, |
| 1508 | |
| 1509 | /* GET elements of VECTOR |
| 1510 | GET is binop (V128, I8) -> I<elem_size> */ |
| 1511 | /* Note: the arm back-end handles only constant second argument. */ |
| 1512 | Iop_GetElem8x16, Iop_GetElem16x8, Iop_GetElem32x4, Iop_GetElem64x2, |
cerion | f887b3e | 2005-09-13 16:34:28 +0000 | [diff] [blame] | 1513 | |
| 1514 | /* DUPLICATING -- copy value to all lanes */ |
sewardj | 2fdd416 | 2010-08-22 12:59:02 +0000 | [diff] [blame] | 1515 | Iop_Dup8x16, Iop_Dup16x8, Iop_Dup32x4, |
| 1516 | |
| 1517 | /* EXTRACT -- copy 16-arg3 highest bytes from arg1 to 16-arg3 lowest bytes |
| 1518 | of result and arg3 lowest bytes of arg2 to arg3 highest bytes of |
| 1519 | result. |
| 1520 | It is a triop: (V128, V128, I8) -> V128 */ |
| 1521 | /* Note: the ARM back end handles only constant arg3 in this operation. */ |
| 1522 | Iop_ExtractV128, |
| 1523 | |
| 1524 | /* REVERSE the order of elements in each Half-words, Words, |
| 1525 | Double-words */ |
| 1526 | /* Examples: |
| 1527 | Reverse32_16x8([a,b,c,d,e,f,g,h]) = [b,a,d,c,f,e,h,g] |
| 1528 | Reverse64_16x8([a,b,c,d,e,f,g,h]) = [d,c,b,a,h,g,f,e] */ |
| 1529 | Iop_Reverse16_8x16, |
| 1530 | Iop_Reverse32_8x16, Iop_Reverse32_16x8, |
| 1531 | Iop_Reverse64_8x16, Iop_Reverse64_16x8, Iop_Reverse64_32x4, |
cerion | f887b3e | 2005-09-13 16:34:28 +0000 | [diff] [blame] | 1532 | |
| 1533 | /* PERMUTING -- copy src bytes to dst, |
sewardj | dc1f913 | 2005-10-22 12:49:49 +0000 | [diff] [blame] | 1534 | as indexed by control vector bytes: |
| 1535 | for i in 0 .. 15 . result[i] = argL[ argR[i] ] |
| 1536 | argR[i] values may only be in the range 0 .. 15, else behaviour |
| 1537 | is undefined. */ |
sewardj | 2fdd416 | 2010-08-22 12:59:02 +0000 | [diff] [blame] | 1538 | Iop_Perm8x16, |
sewardj | d8bca7e | 2012-06-20 11:46:19 +0000 | [diff] [blame] | 1539 | Iop_Perm32x4, /* ditto, except argR values are restricted to 0 .. 3 */ |
sewardj | 2fdd416 | 2010-08-22 12:59:02 +0000 | [diff] [blame] | 1540 | |
sewardj | 78a2059 | 2012-12-13 18:29:56 +0000 | [diff] [blame] | 1541 | /* MISC CONVERSION -- get high bits of each byte lane, a la |
| 1542 | x86/amd64 pmovmskb */ |
sewardj | 0e7d280 | 2013-01-26 11:39:13 +0000 | [diff] [blame] | 1543 | Iop_GetMSBs8x16, /* V128 -> I16 */ |
sewardj | 78a2059 | 2012-12-13 18:29:56 +0000 | [diff] [blame] | 1544 | |
sewardj | 2fdd416 | 2010-08-22 12:59:02 +0000 | [diff] [blame] | 1545 | /* Vector Reciprocal Estimate and Vector Reciprocal Square Root Estimate |
| 1546 | See floating-point equiwalents for details. */ |
sewardj | c4530ae | 2012-05-21 10:18:49 +0000 | [diff] [blame] | 1547 | Iop_Recip32x4, Iop_Rsqrte32x4, |
| 1548 | |
| 1549 | /* ------------------ 256-bit SIMD Integer. ------------------ */ |
| 1550 | |
| 1551 | /* Pack/unpack */ |
sewardj | 4b1cc83 | 2012-06-13 11:10:20 +0000 | [diff] [blame] | 1552 | Iop_V256to64_0, // V256 -> I64, extract least significant lane |
sewardj | c4530ae | 2012-05-21 10:18:49 +0000 | [diff] [blame] | 1553 | Iop_V256to64_1, |
| 1554 | Iop_V256to64_2, |
sewardj | 4b1cc83 | 2012-06-13 11:10:20 +0000 | [diff] [blame] | 1555 | Iop_V256to64_3, // V256 -> I64, extract most significant lane |
sewardj | c4530ae | 2012-05-21 10:18:49 +0000 | [diff] [blame] | 1556 | |
sewardj | 56c3031 | 2012-06-12 08:45:39 +0000 | [diff] [blame] | 1557 | Iop_64x4toV256, // (I64,I64,I64,I64)->V256 |
sewardj | c4530ae | 2012-05-21 10:18:49 +0000 | [diff] [blame] | 1558 | // first arg is most significant lane |
sewardj | 56c3031 | 2012-06-12 08:45:39 +0000 | [diff] [blame] | 1559 | |
sewardj | 4b1cc83 | 2012-06-13 11:10:20 +0000 | [diff] [blame] | 1560 | Iop_V256toV128_0, // V256 -> V128, less significant lane |
| 1561 | Iop_V256toV128_1, // V256 -> V128, more significant lane |
| 1562 | Iop_V128HLtoV256, // (V128,V128)->V256, first arg is most signif |
| 1563 | |
| 1564 | Iop_AndV256, |
sewardj | 2a2bda9 | 2012-06-14 23:32:02 +0000 | [diff] [blame] | 1565 | Iop_OrV256, |
sewardj | 4b1cc83 | 2012-06-13 11:10:20 +0000 | [diff] [blame] | 1566 | Iop_XorV256, |
sewardj | 2a2bda9 | 2012-06-14 23:32:02 +0000 | [diff] [blame] | 1567 | Iop_NotV256, |
sewardj | 4b1cc83 | 2012-06-13 11:10:20 +0000 | [diff] [blame] | 1568 | |
sewardj | 23db8a0 | 2012-06-25 07:46:18 +0000 | [diff] [blame] | 1569 | /* MISC (vector integer cmp != 0) */ |
sewardj | cc3d219 | 2013-03-27 11:37:33 +0000 | [diff] [blame] | 1570 | Iop_CmpNEZ8x32, Iop_CmpNEZ16x16, Iop_CmpNEZ32x8, Iop_CmpNEZ64x4, |
| 1571 | |
| 1572 | Iop_Add8x32, Iop_Add16x16, Iop_Add32x8, Iop_Add64x4, |
| 1573 | Iop_Sub8x32, Iop_Sub16x16, Iop_Sub32x8, Iop_Sub64x4, |
| 1574 | |
| 1575 | Iop_CmpEQ8x32, Iop_CmpEQ16x16, Iop_CmpEQ32x8, Iop_CmpEQ64x4, |
| 1576 | Iop_CmpGT8Sx32, Iop_CmpGT16Sx16, Iop_CmpGT32Sx8, Iop_CmpGT64Sx4, |
| 1577 | |
| 1578 | Iop_ShlN16x16, Iop_ShlN32x8, Iop_ShlN64x4, |
| 1579 | Iop_ShrN16x16, Iop_ShrN32x8, Iop_ShrN64x4, |
| 1580 | Iop_SarN16x16, Iop_SarN32x8, |
| 1581 | |
| 1582 | Iop_Max8Sx32, Iop_Max16Sx16, Iop_Max32Sx8, |
| 1583 | Iop_Max8Ux32, Iop_Max16Ux16, Iop_Max32Ux8, |
| 1584 | Iop_Min8Sx32, Iop_Min16Sx16, Iop_Min32Sx8, |
| 1585 | Iop_Min8Ux32, Iop_Min16Ux16, Iop_Min32Ux8, |
| 1586 | |
| 1587 | Iop_Mul16x16, Iop_Mul32x8, |
| 1588 | Iop_MulHi16Ux16, Iop_MulHi16Sx16, |
| 1589 | |
| 1590 | Iop_QAdd8Ux32, Iop_QAdd16Ux16, |
| 1591 | Iop_QAdd8Sx32, Iop_QAdd16Sx16, |
| 1592 | Iop_QSub8Ux32, Iop_QSub16Ux16, |
| 1593 | Iop_QSub8Sx32, Iop_QSub16Sx16, |
| 1594 | |
| 1595 | Iop_Avg8Ux32, Iop_Avg16Ux16, |
| 1596 | |
| 1597 | Iop_Perm32x8, |
sewardj | 23db8a0 | 2012-06-25 07:46:18 +0000 | [diff] [blame] | 1598 | |
sewardj | 56c3031 | 2012-06-12 08:45:39 +0000 | [diff] [blame] | 1599 | /* ------------------ 256-bit SIMD FP. ------------------ */ |
| 1600 | Iop_Add64Fx4, |
| 1601 | Iop_Sub64Fx4, |
| 1602 | Iop_Mul64Fx4, |
| 1603 | Iop_Div64Fx4, |
| 1604 | Iop_Add32Fx8, |
| 1605 | Iop_Sub32Fx8, |
| 1606 | Iop_Mul32Fx8, |
sewardj | f0ad4f8 | 2012-06-19 06:57:59 +0000 | [diff] [blame] | 1607 | Iop_Div32Fx8, |
| 1608 | |
| 1609 | Iop_Sqrt32Fx8, |
| 1610 | Iop_Sqrt64Fx4, |
sewardj | 8eb7ae8 | 2012-06-24 14:00:27 +0000 | [diff] [blame] | 1611 | Iop_RSqrt32Fx8, |
sewardj | 8209692 | 2012-06-24 14:57:59 +0000 | [diff] [blame] | 1612 | Iop_Recip32Fx8, |
sewardj | 8eb7ae8 | 2012-06-24 14:00:27 +0000 | [diff] [blame] | 1613 | |
| 1614 | Iop_Max32Fx8, Iop_Min32Fx8, |
florian | 2245ce9 | 2012-08-28 16:49:30 +0000 | [diff] [blame] | 1615 | Iop_Max64Fx4, Iop_Min64Fx4, |
| 1616 | Iop_LAST /* must be the last enumerator */ |
sewardj | ac6b712 | 2004-06-27 01:03:57 +0000 | [diff] [blame] | 1617 | } |
| 1618 | IROp; |
sewardj | ec6ad59 | 2004-06-20 12:26:53 +0000 | [diff] [blame] | 1619 | |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 1620 | /* Pretty-print an op. */ |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 1621 | extern void ppIROp ( IROp ); |
sewardj | ec6ad59 | 2004-06-20 12:26:53 +0000 | [diff] [blame] | 1622 | |
sewardj | e3d0d2e | 2004-06-27 10:42:44 +0000 | [diff] [blame] | 1623 | |
florian | 79e5a48 | 2013-06-06 19:12:46 +0000 | [diff] [blame] | 1624 | /* Encoding of IEEE754-specified rounding modes. |
sewardj | f1b5b1a | 2006-02-03 22:54:17 +0000 | [diff] [blame] | 1625 | Note, various front and back ends rely on the actual numerical |
| 1626 | values of these, so do not change them. */ |
sewardj | c9868d7 | 2004-09-12 19:19:17 +0000 | [diff] [blame] | 1627 | typedef |
sewardj | f1b5b1a | 2006-02-03 22:54:17 +0000 | [diff] [blame] | 1628 | enum { |
florian | 79e5a48 | 2013-06-06 19:12:46 +0000 | [diff] [blame] | 1629 | Irrm_NEAREST = 0, // Round to nearest, ties to even |
| 1630 | Irrm_NegINF = 1, // Round to negative infinity |
| 1631 | Irrm_PosINF = 2, // Round to positive infinity |
| 1632 | Irrm_ZERO = 3, // Round toward zero |
| 1633 | Irrm_NEAREST_TIE_AWAY_0 = 4, // Round to nearest, ties away from 0 |
| 1634 | Irrm_PREPARE_SHORTER = 5, // Round to prepare for storter |
| 1635 | // precision |
| 1636 | Irrm_AWAY_FROM_ZERO = 6, // Round to away from 0 |
| 1637 | Irrm_NEAREST_TIE_TOWARD_0 = 7 // Round to nearest, ties towards 0 |
sewardj | f1b5b1a | 2006-02-03 22:54:17 +0000 | [diff] [blame] | 1638 | } |
sewardj | c9868d7 | 2004-09-12 19:19:17 +0000 | [diff] [blame] | 1639 | IRRoundingMode; |
| 1640 | |
florian | daa4084 | 2012-12-21 20:24:24 +0000 | [diff] [blame] | 1641 | /* Binary floating point comparison result values. |
sewardj | c9868d7 | 2004-09-12 19:19:17 +0000 | [diff] [blame] | 1642 | This is also derived from what IA32 does. */ |
| 1643 | typedef |
| 1644 | enum { |
| 1645 | Ircr_UN = 0x45, |
| 1646 | Ircr_LT = 0x01, |
| 1647 | Ircr_GT = 0x00, |
| 1648 | Ircr_EQ = 0x40 |
| 1649 | } |
florian | daa4084 | 2012-12-21 20:24:24 +0000 | [diff] [blame] | 1650 | IRCmpFResult; |
sewardj | c9868d7 | 2004-09-12 19:19:17 +0000 | [diff] [blame] | 1651 | |
florian | daa4084 | 2012-12-21 20:24:24 +0000 | [diff] [blame] | 1652 | typedef IRCmpFResult IRCmpF32Result; |
| 1653 | typedef IRCmpFResult IRCmpF64Result; |
| 1654 | typedef IRCmpFResult IRCmpF128Result; |
| 1655 | |
| 1656 | /* Decimal floating point result values. */ |
| 1657 | typedef IRCmpFResult IRCmpDResult; |
| 1658 | typedef IRCmpDResult IRCmpD64Result; |
| 1659 | typedef IRCmpDResult IRCmpD128Result; |
sewardj | c9868d7 | 2004-09-12 19:19:17 +0000 | [diff] [blame] | 1660 | |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 1661 | /* ------------------ Expressions ------------------ */ |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 1662 | |
florian | eadea2e | 2012-06-06 12:53:14 +0000 | [diff] [blame] | 1663 | typedef struct _IRQop IRQop; /* forward declaration */ |
| 1664 | typedef struct _IRTriop IRTriop; /* forward declaration */ |
florian | 96d7cc3 | 2012-06-01 20:41:24 +0000 | [diff] [blame] | 1665 | |
| 1666 | |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 1667 | /* The different kinds of expressions. Their meaning is explained below |
| 1668 | in the comments for IRExpr. */ |
sewardj | e3d0d2e | 2004-06-27 10:42:44 +0000 | [diff] [blame] | 1669 | typedef |
sewardj | b3bce0e | 2004-09-14 23:20:10 +0000 | [diff] [blame] | 1670 | enum { |
sewardj | cfe046e | 2013-01-17 14:23:53 +0000 | [diff] [blame] | 1671 | Iex_Binder=0x1900, |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 1672 | Iex_Get, |
| 1673 | Iex_GetI, |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 1674 | Iex_RdTmp, |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 1675 | Iex_Qop, |
| 1676 | Iex_Triop, |
| 1677 | Iex_Binop, |
| 1678 | Iex_Unop, |
| 1679 | Iex_Load, |
| 1680 | Iex_Const, |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 1681 | Iex_ITE, |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 1682 | Iex_CCall |
sewardj | b3bce0e | 2004-09-14 23:20:10 +0000 | [diff] [blame] | 1683 | } |
sewardj | e3d0d2e | 2004-06-27 10:42:44 +0000 | [diff] [blame] | 1684 | IRExprTag; |
| 1685 | |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 1686 | /* An expression. Stored as a tagged union. 'tag' indicates what kind |
| 1687 | of expression this is. 'Iex' is the union that holds the fields. If |
| 1688 | an IRExpr 'e' has e.tag equal to Iex_Load, then it's a load |
| 1689 | expression, and the fields can be accessed with |
| 1690 | 'e.Iex.Load.<fieldname>'. |
| 1691 | |
| 1692 | For each kind of expression, we show what it looks like when |
| 1693 | pretty-printed with ppIRExpr(). |
| 1694 | */ |
| 1695 | typedef |
| 1696 | struct _IRExpr |
sewardj | e3d0d2e | 2004-06-27 10:42:44 +0000 | [diff] [blame] | 1697 | IRExpr; |
| 1698 | |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 1699 | struct _IRExpr { |
| 1700 | IRExprTag tag; |
| 1701 | union { |
| 1702 | /* Used only in pattern matching within Vex. Should not be seen |
| 1703 | outside of Vex. */ |
| 1704 | struct { |
| 1705 | Int binder; |
| 1706 | } Binder; |
| 1707 | |
| 1708 | /* Read a guest register, at a fixed offset in the guest state. |
| 1709 | ppIRExpr output: GET:<ty>(<offset>), eg. GET:I32(0) |
| 1710 | */ |
| 1711 | struct { |
| 1712 | Int offset; /* Offset into the guest state */ |
| 1713 | IRType ty; /* Type of the value being read */ |
| 1714 | } Get; |
| 1715 | |
| 1716 | /* Read a guest register at a non-fixed offset in the guest |
| 1717 | state. This allows circular indexing into parts of the guest |
| 1718 | state, which is essential for modelling situations where the |
| 1719 | identity of guest registers is not known until run time. One |
| 1720 | example is the x87 FP register stack. |
| 1721 | |
| 1722 | The part of the guest state to be treated as a circular array |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 1723 | is described in the IRRegArray 'descr' field. It holds the |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 1724 | offset of the first element in the array, the type of each |
| 1725 | element, and the number of elements. |
| 1726 | |
| 1727 | The array index is indicated rather indirectly, in a way |
| 1728 | which makes optimisation easy: as the sum of variable part |
| 1729 | (the 'ix' field) and a constant offset (the 'bias' field). |
| 1730 | |
| 1731 | Since the indexing is circular, the actual array index to use |
| 1732 | is computed as (ix + bias) % num-of-elems-in-the-array. |
| 1733 | |
| 1734 | Here's an example. The description |
| 1735 | |
| 1736 | (96:8xF64)[t39,-7] |
| 1737 | |
| 1738 | describes an array of 8 F64-typed values, the |
| 1739 | guest-state-offset of the first being 96. This array is |
| 1740 | being indexed at (t39 - 7) % 8. |
| 1741 | |
| 1742 | It is important to get the array size/type exactly correct |
| 1743 | since IR optimisation looks closely at such info in order to |
| 1744 | establish aliasing/non-aliasing between seperate GetI and |
| 1745 | PutI events, which is used to establish when they can be |
| 1746 | reordered, etc. Putting incorrect info in will lead to |
| 1747 | obscure IR optimisation bugs. |
| 1748 | |
| 1749 | ppIRExpr output: GETI<descr>[<ix>,<bias] |
| 1750 | eg. GETI(128:8xI8)[t1,0] |
| 1751 | */ |
| 1752 | struct { |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 1753 | IRRegArray* descr; /* Part of guest state treated as circular */ |
| 1754 | IRExpr* ix; /* Variable part of index into array */ |
| 1755 | Int bias; /* Constant offset part of index into array */ |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 1756 | } GetI; |
| 1757 | |
| 1758 | /* The value held by a temporary. |
| 1759 | ppIRExpr output: t<tmp>, eg. t1 |
| 1760 | */ |
| 1761 | struct { |
| 1762 | IRTemp tmp; /* The temporary number */ |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 1763 | } RdTmp; |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 1764 | |
| 1765 | /* A quaternary operation. |
| 1766 | ppIRExpr output: <op>(<arg1>, <arg2>, <arg3>, <arg4>), |
| 1767 | eg. MAddF64r32(t1, t2, t3, t4) |
| 1768 | */ |
| 1769 | struct { |
florian | 96d7cc3 | 2012-06-01 20:41:24 +0000 | [diff] [blame] | 1770 | IRQop* details; |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 1771 | } Qop; |
| 1772 | |
| 1773 | /* A ternary operation. |
| 1774 | ppIRExpr output: <op>(<arg1>, <arg2>, <arg3>), |
| 1775 | eg. MulF64(1, 2.0, 3.0) |
| 1776 | */ |
| 1777 | struct { |
florian | 420bfa9 | 2012-06-02 20:29:22 +0000 | [diff] [blame] | 1778 | IRTriop* details; |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 1779 | } Triop; |
| 1780 | |
| 1781 | /* A binary operation. |
| 1782 | ppIRExpr output: <op>(<arg1>, <arg2>), eg. Add32(t1,t2) |
| 1783 | */ |
| 1784 | struct { |
| 1785 | IROp op; /* op-code */ |
| 1786 | IRExpr* arg1; /* operand 1 */ |
| 1787 | IRExpr* arg2; /* operand 2 */ |
| 1788 | } Binop; |
| 1789 | |
| 1790 | /* A unary operation. |
| 1791 | ppIRExpr output: <op>(<arg>), eg. Neg8(t1) |
| 1792 | */ |
| 1793 | struct { |
| 1794 | IROp op; /* op-code */ |
| 1795 | IRExpr* arg; /* operand */ |
| 1796 | } Unop; |
| 1797 | |
sewardj | e768e92 | 2009-11-26 17:17:37 +0000 | [diff] [blame] | 1798 | /* A load from memory -- a normal load, not a load-linked. |
| 1799 | Load-Linkeds (and Store-Conditionals) are instead represented |
| 1800 | by IRStmt.LLSC since Load-Linkeds have side effects and so |
| 1801 | are not semantically valid IRExpr's. |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 1802 | ppIRExpr output: LD<end>:<ty>(<addr>), eg. LDle:I32(t1) |
| 1803 | */ |
| 1804 | struct { |
| 1805 | IREndness end; /* Endian-ness of the load */ |
| 1806 | IRType ty; /* Type of the loaded value */ |
| 1807 | IRExpr* addr; /* Address being loaded from */ |
| 1808 | } Load; |
| 1809 | |
| 1810 | /* A constant-valued expression. |
| 1811 | ppIRExpr output: <con>, eg. 0x4:I32 |
| 1812 | */ |
| 1813 | struct { |
| 1814 | IRConst* con; /* The constant itself */ |
| 1815 | } Const; |
| 1816 | |
| 1817 | /* A call to a pure (no side-effects) helper C function. |
| 1818 | |
| 1819 | With the 'cee' field, 'name' is the function's name. It is |
| 1820 | only used for pretty-printing purposes. The address to call |
| 1821 | (host address, of course) is stored in the 'addr' field |
| 1822 | inside 'cee'. |
| 1823 | |
| 1824 | The 'args' field is a NULL-terminated array of arguments. |
| 1825 | The stated return IRType, and the implied argument types, |
| 1826 | must match that of the function being called well enough so |
| 1827 | that the back end can actually generate correct code for the |
| 1828 | call. |
| 1829 | |
| 1830 | The called function **must** satisfy the following: |
| 1831 | |
| 1832 | * no side effects -- must be a pure function, the result of |
| 1833 | which depends only on the passed parameters. |
| 1834 | |
| 1835 | * it may not look at, nor modify, any of the guest state |
| 1836 | since that would hide guest state transitions from |
| 1837 | instrumenters |
| 1838 | |
| 1839 | * it may not access guest memory, since that would hide |
| 1840 | guest memory transactions from the instrumenters |
| 1841 | |
florian | 52af7bc | 2012-05-12 03:44:49 +0000 | [diff] [blame] | 1842 | * it must not assume that arguments are being evaluated in a |
| 1843 | particular order. The oder of evaluation is unspecified. |
| 1844 | |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 1845 | This is restrictive, but makes the semantics clean, and does |
| 1846 | not interfere with IR optimisation. |
| 1847 | |
| 1848 | If you want to call a helper which can mess with guest state |
| 1849 | and/or memory, instead use Ist_Dirty. This is a lot more |
| 1850 | flexible, but you have to give a bunch of details about what |
| 1851 | the helper does (and you better be telling the truth, |
| 1852 | otherwise any derived instrumentation will be wrong). Also |
| 1853 | Ist_Dirty inhibits various IR optimisations and so can cause |
| 1854 | quite poor code to be generated. Try to avoid it. |
| 1855 | |
| 1856 | ppIRExpr output: <cee>(<args>):<retty> |
| 1857 | eg. foo{0x80489304}(t1, t2):I32 |
| 1858 | */ |
| 1859 | struct { |
| 1860 | IRCallee* cee; /* Function to call. */ |
| 1861 | IRType retty; /* Type of return value. */ |
| 1862 | IRExpr** args; /* Vector of argument expressions. */ |
| 1863 | } CCall; |
| 1864 | |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 1865 | /* A ternary if-then-else operator. It returns iftrue if cond is |
| 1866 | nonzero, iffalse otherwise. Note that it is STRICT, ie. both |
| 1867 | iftrue and iffalse are evaluated in all cases. |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 1868 | |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 1869 | ppIRExpr output: ITE(<cond>,<iftrue>,<iffalse>), |
| 1870 | eg. ITE(t6,t7,t8) |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 1871 | */ |
| 1872 | struct { |
| 1873 | IRExpr* cond; /* Condition */ |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 1874 | IRExpr* iftrue; /* True expression */ |
| 1875 | IRExpr* iffalse; /* False expression */ |
| 1876 | } ITE; |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 1877 | } Iex; |
| 1878 | }; |
| 1879 | |
sewardj | cfe046e | 2013-01-17 14:23:53 +0000 | [diff] [blame] | 1880 | /* Expression auxiliaries: a ternary expression. */ |
florian | 420bfa9 | 2012-06-02 20:29:22 +0000 | [diff] [blame] | 1881 | struct _IRTriop { |
| 1882 | IROp op; /* op-code */ |
| 1883 | IRExpr* arg1; /* operand 1 */ |
| 1884 | IRExpr* arg2; /* operand 2 */ |
| 1885 | IRExpr* arg3; /* operand 3 */ |
| 1886 | }; |
| 1887 | |
sewardj | cfe046e | 2013-01-17 14:23:53 +0000 | [diff] [blame] | 1888 | /* Expression auxiliaries: a quarternary expression. */ |
florian | 96d7cc3 | 2012-06-01 20:41:24 +0000 | [diff] [blame] | 1889 | struct _IRQop { |
| 1890 | IROp op; /* op-code */ |
| 1891 | IRExpr* arg1; /* operand 1 */ |
| 1892 | IRExpr* arg2; /* operand 2 */ |
| 1893 | IRExpr* arg3; /* operand 3 */ |
| 1894 | IRExpr* arg4; /* operand 4 */ |
| 1895 | }; |
| 1896 | |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 1897 | /* Expression constructors. */ |
sewardj | 443cd9d | 2004-07-18 23:06:45 +0000 | [diff] [blame] | 1898 | extern IRExpr* IRExpr_Binder ( Int binder ); |
| 1899 | extern IRExpr* IRExpr_Get ( Int off, IRType ty ); |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 1900 | extern IRExpr* IRExpr_GetI ( IRRegArray* descr, IRExpr* ix, Int bias ); |
| 1901 | extern IRExpr* IRExpr_RdTmp ( IRTemp tmp ); |
sewardj | 40c8026 | 2006-02-08 19:30:46 +0000 | [diff] [blame] | 1902 | extern IRExpr* IRExpr_Qop ( IROp op, IRExpr* arg1, IRExpr* arg2, |
| 1903 | IRExpr* arg3, IRExpr* arg4 ); |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 1904 | extern IRExpr* IRExpr_Triop ( IROp op, IRExpr* arg1, |
| 1905 | IRExpr* arg2, IRExpr* arg3 ); |
sewardj | 443cd9d | 2004-07-18 23:06:45 +0000 | [diff] [blame] | 1906 | extern IRExpr* IRExpr_Binop ( IROp op, IRExpr* arg1, IRExpr* arg2 ); |
| 1907 | extern IRExpr* IRExpr_Unop ( IROp op, IRExpr* arg ); |
sewardj | e768e92 | 2009-11-26 17:17:37 +0000 | [diff] [blame] | 1908 | extern IRExpr* IRExpr_Load ( IREndness end, IRType ty, IRExpr* addr ); |
sewardj | 443cd9d | 2004-07-18 23:06:45 +0000 | [diff] [blame] | 1909 | extern IRExpr* IRExpr_Const ( IRConst* con ); |
sewardj | 8ea867b | 2004-10-30 19:03:02 +0000 | [diff] [blame] | 1910 | extern IRExpr* IRExpr_CCall ( IRCallee* cee, IRType retty, IRExpr** args ); |
florian | 99dd03e | 2013-01-29 03:56:06 +0000 | [diff] [blame] | 1911 | extern IRExpr* IRExpr_ITE ( IRExpr* cond, IRExpr* iftrue, IRExpr* iffalse ); |
sewardj | e3d0d2e | 2004-06-27 10:42:44 +0000 | [diff] [blame] | 1912 | |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 1913 | /* Deep-copy an IRExpr. */ |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 1914 | extern IRExpr* deepCopyIRExpr ( IRExpr* ); |
sewardj | 695cff9 | 2004-10-13 14:50:14 +0000 | [diff] [blame] | 1915 | |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 1916 | /* Pretty-print an IRExpr. */ |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 1917 | extern void ppIRExpr ( IRExpr* ); |
sewardj | ec6ad59 | 2004-06-20 12:26:53 +0000 | [diff] [blame] | 1918 | |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 1919 | /* NULL-terminated IRExpr vector constructors, suitable for |
| 1920 | use as arg lists in clean/dirty helper calls. */ |
sewardj | c5fc7aa | 2004-10-27 23:00:55 +0000 | [diff] [blame] | 1921 | extern IRExpr** mkIRExprVec_0 ( void ); |
sewardj | f965526 | 2004-10-31 20:02:16 +0000 | [diff] [blame] | 1922 | extern IRExpr** mkIRExprVec_1 ( IRExpr* ); |
| 1923 | extern IRExpr** mkIRExprVec_2 ( IRExpr*, IRExpr* ); |
| 1924 | extern IRExpr** mkIRExprVec_3 ( IRExpr*, IRExpr*, IRExpr* ); |
| 1925 | extern IRExpr** mkIRExprVec_4 ( IRExpr*, IRExpr*, IRExpr*, IRExpr* ); |
sewardj | 78ec32b | 2007-01-08 05:09:55 +0000 | [diff] [blame] | 1926 | extern IRExpr** mkIRExprVec_5 ( IRExpr*, IRExpr*, IRExpr*, IRExpr*, |
| 1927 | IRExpr* ); |
| 1928 | extern IRExpr** mkIRExprVec_6 ( IRExpr*, IRExpr*, IRExpr*, IRExpr*, |
| 1929 | IRExpr*, IRExpr* ); |
| 1930 | extern IRExpr** mkIRExprVec_7 ( IRExpr*, IRExpr*, IRExpr*, IRExpr*, |
sewardj | f32c67d | 2004-11-08 13:10:44 +0000 | [diff] [blame] | 1931 | IRExpr*, IRExpr*, IRExpr* ); |
sewardj | 2fdd416 | 2010-08-22 12:59:02 +0000 | [diff] [blame] | 1932 | extern IRExpr** mkIRExprVec_8 ( IRExpr*, IRExpr*, IRExpr*, IRExpr*, |
| 1933 | IRExpr*, IRExpr*, IRExpr*, IRExpr*); |
sewardj | c5fc7aa | 2004-10-27 23:00:55 +0000 | [diff] [blame] | 1934 | |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 1935 | /* IRExpr copiers: |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 1936 | - shallowCopy: shallow-copy (ie. create a new vector that shares the |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 1937 | elements with the original). |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 1938 | - deepCopy: deep-copy (ie. create a completely new vector). */ |
| 1939 | extern IRExpr** shallowCopyIRExprVec ( IRExpr** ); |
| 1940 | extern IRExpr** deepCopyIRExprVec ( IRExpr** ); |
sewardj | c5fc7aa | 2004-10-27 23:00:55 +0000 | [diff] [blame] | 1941 | |
sewardj | f965526 | 2004-10-31 20:02:16 +0000 | [diff] [blame] | 1942 | /* Make a constant expression from the given host word taking into |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 1943 | account (of course) the host word size. */ |
sewardj | 49651f4 | 2004-10-28 22:11:04 +0000 | [diff] [blame] | 1944 | extern IRExpr* mkIRExpr_HWord ( HWord ); |
| 1945 | |
sewardj | f965526 | 2004-10-31 20:02:16 +0000 | [diff] [blame] | 1946 | /* Convenience function for constructing clean helper calls. */ |
| 1947 | extern |
| 1948 | IRExpr* mkIRExprCCall ( IRType retty, |
florian | 1ff4756 | 2012-10-21 02:09:51 +0000 | [diff] [blame] | 1949 | Int regparms, const HChar* name, void* addr, |
sewardj | f965526 | 2004-10-31 20:02:16 +0000 | [diff] [blame] | 1950 | IRExpr** args ); |
| 1951 | |
sewardj | 49651f4 | 2004-10-28 22:11:04 +0000 | [diff] [blame] | 1952 | |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 1953 | /* Convenience functions for atoms (IRExprs which are either Iex_Tmp or |
| 1954 | * Iex_Const). */ |
sewardj | 496a58d | 2005-03-20 18:44:44 +0000 | [diff] [blame] | 1955 | static inline Bool isIRAtom ( IRExpr* e ) { |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 1956 | return toBool(e->tag == Iex_RdTmp || e->tag == Iex_Const); |
sewardj | 49651f4 | 2004-10-28 22:11:04 +0000 | [diff] [blame] | 1957 | } |
| 1958 | |
sewardj | 496a58d | 2005-03-20 18:44:44 +0000 | [diff] [blame] | 1959 | /* Are these two IR atoms identical? Causes an assertion |
| 1960 | failure if they are passed non-atoms. */ |
| 1961 | extern Bool eqIRAtom ( IRExpr*, IRExpr* ); |
| 1962 | |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 1963 | |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 1964 | /* ------------------ Jump kinds ------------------ */ |
| 1965 | |
| 1966 | /* This describes hints which can be passed to the dispatcher at guest |
| 1967 | control-flow transfer points. |
sewardj | 7ce9d15 | 2005-03-15 16:54:13 +0000 | [diff] [blame] | 1968 | |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 1969 | Re Ijk_TInval: the guest state _must_ have two pseudo-registers, |
| 1970 | guest_TISTART and guest_TILEN, which specify the start and length |
| 1971 | of the region to be invalidated. These are both the size of a |
| 1972 | guest word. It is the responsibility of the relevant toIR.c to |
| 1973 | ensure that these are filled in with suitable values before issuing |
| 1974 | a jump of kind Ijk_TInval. |
sewardj | 9dd9cf1 | 2006-01-20 14:13:55 +0000 | [diff] [blame] | 1975 | |
| 1976 | Re Ijk_EmWarn and Ijk_EmFail: the guest state must have a |
florian | 6ef84be | 2012-08-26 03:20:07 +0000 | [diff] [blame] | 1977 | pseudo-register guest_EMNOTE, which is 32-bits regardless of the |
| 1978 | host or guest word size. That register should be made to hold a |
| 1979 | VexEmNote value to indicate the reason for the exit. |
sewardj | 9dd9cf1 | 2006-01-20 14:13:55 +0000 | [diff] [blame] | 1980 | |
| 1981 | In the case of Ijk_EmFail, the exit is fatal (Vex-generated code |
| 1982 | cannot continue) and so the jump destination can be anything. |
sewardj | e86310f | 2009-03-19 22:21:40 +0000 | [diff] [blame] | 1983 | |
| 1984 | Re Ijk_Sys_ (syscall jumps): the guest state must have a |
| 1985 | pseudo-register guest_IP_AT_SYSCALL, which is the size of a guest |
| 1986 | word. Front ends should set this to be the IP at the most recently |
| 1987 | executed kernel-entering (system call) instruction. This makes it |
| 1988 | very much easier (viz, actually possible at all) to back up the |
| 1989 | guest to restart a syscall that has been interrupted by a signal. |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 1990 | */ |
| 1991 | typedef |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 1992 | enum { |
sewardj | cfe046e | 2013-01-17 14:23:53 +0000 | [diff] [blame] | 1993 | Ijk_INVALID=0x1A00, |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 1994 | Ijk_Boring, /* not interesting; just goto next */ |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 1995 | Ijk_Call, /* guest is doing a call */ |
| 1996 | Ijk_Ret, /* guest is doing a return */ |
| 1997 | Ijk_ClientReq, /* do guest client req before continuing */ |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 1998 | Ijk_Yield, /* client is yielding to thread scheduler */ |
sewardj | 52444cb | 2004-12-13 14:09:01 +0000 | [diff] [blame] | 1999 | Ijk_EmWarn, /* report emulation warning before continuing */ |
sewardj | 9dd9cf1 | 2006-01-20 14:13:55 +0000 | [diff] [blame] | 2000 | Ijk_EmFail, /* emulation critical (FATAL) error; give up */ |
florian | 0b39008 | 2012-08-25 02:01:25 +0000 | [diff] [blame] | 2001 | Ijk_NoDecode, /* current instruction cannot be decoded */ |
sewardj | 7ce9d15 | 2005-03-15 16:54:13 +0000 | [diff] [blame] | 2002 | Ijk_MapFail, /* Vex-provided address translation failed */ |
sewardj | f07ed03 | 2005-08-07 14:48:03 +0000 | [diff] [blame] | 2003 | Ijk_TInval, /* Invalidate translations before continuing. */ |
sewardj | ce02aa7 | 2006-01-12 12:27:58 +0000 | [diff] [blame] | 2004 | Ijk_NoRedir, /* Jump to un-redirected guest addr */ |
sewardj | 0f50004 | 2007-08-29 09:09:17 +0000 | [diff] [blame] | 2005 | Ijk_SigTRAP, /* current instruction synths SIGTRAP */ |
| 2006 | Ijk_SigSEGV, /* current instruction synths SIGSEGV */ |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 2007 | Ijk_SigBUS, /* current instruction synths SIGBUS */ |
petarj | a6a1986 | 2012-10-19 14:55:58 +0000 | [diff] [blame] | 2008 | Ijk_SigFPE_IntDiv, /* current instruction synths SIGFPE - IntDiv */ |
| 2009 | Ijk_SigFPE_IntOvf, /* current instruction synths SIGFPE - IntOvf */ |
sewardj | 4fa325a | 2005-11-03 13:27:24 +0000 | [diff] [blame] | 2010 | /* Unfortunately, various guest-dependent syscall kinds. They |
| 2011 | all mean: do a syscall before continuing. */ |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 2012 | Ijk_Sys_syscall, /* amd64 'syscall', ppc 'sc', arm 'svc #0' */ |
sewardj | 4fa325a | 2005-11-03 13:27:24 +0000 | [diff] [blame] | 2013 | Ijk_Sys_int32, /* amd64/x86 'int $0x20' */ |
| 2014 | Ijk_Sys_int128, /* amd64/x86 'int $0x80' */ |
sewardj | d660d41 | 2008-12-03 21:29:59 +0000 | [diff] [blame] | 2015 | Ijk_Sys_int129, /* amd64/x86 'int $0x81' */ |
| 2016 | Ijk_Sys_int130, /* amd64/x86 'int $0x82' */ |
sewardj | 4fa325a | 2005-11-03 13:27:24 +0000 | [diff] [blame] | 2017 | Ijk_Sys_sysenter /* x86 'sysenter'. guest_EIP becomes |
| 2018 | invalid at the point this happens. */ |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 2019 | } |
| 2020 | IRJumpKind; |
| 2021 | |
| 2022 | extern void ppIRJumpKind ( IRJumpKind ); |
| 2023 | |
| 2024 | |
sewardj | b3bce0e | 2004-09-14 23:20:10 +0000 | [diff] [blame] | 2025 | /* ------------------ Dirty helper calls ------------------ */ |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 2026 | |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 2027 | /* A dirty call is a flexible mechanism for calling (possibly |
| 2028 | conditionally) a helper function or procedure. The helper function |
| 2029 | may read, write or modify client memory, and may read, write or |
| 2030 | modify client state. It can take arguments and optionally return a |
| 2031 | value. It may return different results and/or do different things |
| 2032 | when called repeatedly with the same arguments, by means of storing |
| 2033 | private state. |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 2034 | |
sewardj | c5fc7aa | 2004-10-27 23:00:55 +0000 | [diff] [blame] | 2035 | If a value is returned, it is assigned to the nominated return |
| 2036 | temporary. |
sewardj | b3bce0e | 2004-09-14 23:20:10 +0000 | [diff] [blame] | 2037 | |
| 2038 | Dirty calls are statements rather than expressions for obvious |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 2039 | reasons. If a dirty call is marked as writing guest state, any |
sewardj | cfe046e | 2013-01-17 14:23:53 +0000 | [diff] [blame] | 2040 | pre-existing values derived from the written parts of the guest |
| 2041 | state are invalid. Similarly, if the dirty call is stated as |
| 2042 | writing memory, any pre-existing loaded values are invalidated by |
| 2043 | it. |
sewardj | b3bce0e | 2004-09-14 23:20:10 +0000 | [diff] [blame] | 2044 | |
| 2045 | In order that instrumentation is possible, the call must state, and |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 2046 | state correctly: |
sewardj | b3bce0e | 2004-09-14 23:20:10 +0000 | [diff] [blame] | 2047 | |
sewardj | cfe046e | 2013-01-17 14:23:53 +0000 | [diff] [blame] | 2048 | * Whether it reads, writes or modifies memory, and if so where. |
sewardj | b3bce0e | 2004-09-14 23:20:10 +0000 | [diff] [blame] | 2049 | |
sewardj | cfe046e | 2013-01-17 14:23:53 +0000 | [diff] [blame] | 2050 | * Whether it reads, writes or modifies guest state, and if so which |
| 2051 | pieces. Several pieces may be stated, and their extents must be |
| 2052 | known at translation-time. Each piece is allowed to repeat some |
| 2053 | number of times at a fixed interval, if required. |
sewardj | c5fc7aa | 2004-10-27 23:00:55 +0000 | [diff] [blame] | 2054 | |
| 2055 | Normally, code is generated to pass just the args to the helper. |
| 2056 | However, if .needsBBP is set, then an extra first argument is |
| 2057 | passed, which is the baseblock pointer, so that the callee can |
| 2058 | access the guest state. It is invalid for .nFxState to be zero |
| 2059 | but .needsBBP to be True, since .nFxState==0 is a claim that the |
| 2060 | call does not access guest state. |
sewardj | b8385d8 | 2004-11-02 01:34:15 +0000 | [diff] [blame] | 2061 | |
| 2062 | IMPORTANT NOTE re GUARDS: Dirty calls are strict, very strict. The |
sewardj | cfe046e | 2013-01-17 14:23:53 +0000 | [diff] [blame] | 2063 | arguments and 'mFx' are evaluated REGARDLESS of the guard value. |
| 2064 | The order of argument evaluation is unspecified. The guard |
| 2065 | expression is evaluated AFTER the arguments and 'mFx' have been |
| 2066 | evaluated. 'mFx' is expected (by Memcheck) to be a defined value |
| 2067 | even if the guard evaluates to false. |
sewardj | e87b484 | 2004-07-10 12:23:30 +0000 | [diff] [blame] | 2068 | */ |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 2069 | |
sewardj | a0e83b0 | 2005-01-06 12:36:38 +0000 | [diff] [blame] | 2070 | #define VEX_N_FXSTATE 7 /* enough for FXSAVE/FXRSTOR on x86 */ |
sewardj | b3bce0e | 2004-09-14 23:20:10 +0000 | [diff] [blame] | 2071 | |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 2072 | /* Effects on resources (eg. registers, memory locations) */ |
sewardj | b3bce0e | 2004-09-14 23:20:10 +0000 | [diff] [blame] | 2073 | typedef |
| 2074 | enum { |
sewardj | cfe046e | 2013-01-17 14:23:53 +0000 | [diff] [blame] | 2075 | Ifx_None=0x1B00, /* no effect */ |
sewardj | 17442fe | 2004-09-20 14:54:28 +0000 | [diff] [blame] | 2076 | Ifx_Read, /* reads the resource */ |
| 2077 | Ifx_Write, /* writes the resource */ |
| 2078 | Ifx_Modify, /* modifies the resource */ |
sewardj | b3bce0e | 2004-09-14 23:20:10 +0000 | [diff] [blame] | 2079 | } |
| 2080 | IREffect; |
| 2081 | |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 2082 | /* Pretty-print an IREffect */ |
sewardj | b3bce0e | 2004-09-14 23:20:10 +0000 | [diff] [blame] | 2083 | extern void ppIREffect ( IREffect ); |
| 2084 | |
sewardj | b3bce0e | 2004-09-14 23:20:10 +0000 | [diff] [blame] | 2085 | typedef |
sewardj | c9069f2 | 2012-06-01 16:09:50 +0000 | [diff] [blame] | 2086 | struct _IRDirty { |
sewardj | f5dfa3b | 2012-07-10 16:41:46 +0000 | [diff] [blame] | 2087 | /* What to call, and details of args/results. .guard must be |
sewardj | cfe046e | 2013-01-17 14:23:53 +0000 | [diff] [blame] | 2088 | non-NULL. If .tmp is not IRTemp_INVALID, then the call |
| 2089 | returns a result which is placed in .tmp. If at runtime the |
| 2090 | guard evaluates to false, .tmp has an 0x555..555 bit pattern |
| 2091 | written to it. Hence conditional calls that assign .tmp are |
sewardj | f5dfa3b | 2012-07-10 16:41:46 +0000 | [diff] [blame] | 2092 | allowed. */ |
sewardj | 8ea867b | 2004-10-30 19:03:02 +0000 | [diff] [blame] | 2093 | IRCallee* cee; /* where to call */ |
sewardj | b8385d8 | 2004-11-02 01:34:15 +0000 | [diff] [blame] | 2094 | IRExpr* guard; /* :: Ity_Bit. Controls whether call happens */ |
sewardj | 8ea867b | 2004-10-30 19:03:02 +0000 | [diff] [blame] | 2095 | IRExpr** args; /* arg list, ends in NULL */ |
sewardj | 92d168d | 2004-11-15 14:22:12 +0000 | [diff] [blame] | 2096 | IRTemp tmp; /* to assign result to, or IRTemp_INVALID if none */ |
sewardj | b3bce0e | 2004-09-14 23:20:10 +0000 | [diff] [blame] | 2097 | |
| 2098 | /* Mem effects; we allow only one R/W/M region to be stated */ |
sewardj | 8ea867b | 2004-10-30 19:03:02 +0000 | [diff] [blame] | 2099 | IREffect mFx; /* indicates memory effects, if any */ |
| 2100 | IRExpr* mAddr; /* of access, or NULL if mFx==Ifx_None */ |
| 2101 | Int mSize; /* of access, or zero if mFx==Ifx_None */ |
sewardj | b3bce0e | 2004-09-14 23:20:10 +0000 | [diff] [blame] | 2102 | |
| 2103 | /* Guest state effects; up to N allowed */ |
sewardj | c5fc7aa | 2004-10-27 23:00:55 +0000 | [diff] [blame] | 2104 | Bool needsBBP; /* True => also pass guest state ptr to callee */ |
| 2105 | Int nFxState; /* must be 0 .. VEX_N_FXSTATE */ |
sewardj | b3bce0e | 2004-09-14 23:20:10 +0000 | [diff] [blame] | 2106 | struct { |
sewardj | c9069f2 | 2012-06-01 16:09:50 +0000 | [diff] [blame] | 2107 | IREffect fx:16; /* read, write or modify? Ifx_None is invalid. */ |
| 2108 | UShort offset; |
| 2109 | UShort size; |
| 2110 | UChar nRepeats; |
| 2111 | UChar repeatLen; |
sewardj | b3bce0e | 2004-09-14 23:20:10 +0000 | [diff] [blame] | 2112 | } fxState[VEX_N_FXSTATE]; |
sewardj | c9069f2 | 2012-06-01 16:09:50 +0000 | [diff] [blame] | 2113 | /* The access can be repeated, as specified by nRepeats and |
| 2114 | repeatLen. To describe only a single access, nRepeats and |
| 2115 | repeatLen should be zero. Otherwise, repeatLen must be a |
| 2116 | multiple of size and greater than size. */ |
| 2117 | /* Overall, the parts of the guest state denoted by (offset, |
| 2118 | size, nRepeats, repeatLen) is |
| 2119 | [offset, +size) |
| 2120 | and, if nRepeats > 0, |
| 2121 | for (i = 1; i <= nRepeats; i++) |
| 2122 | [offset + i * repeatLen, +size) |
| 2123 | A convenient way to enumerate all segments is therefore |
| 2124 | for (i = 0; i < 1 + nRepeats; i++) |
| 2125 | [offset + i * repeatLen, +size) |
| 2126 | */ |
sewardj | b3bce0e | 2004-09-14 23:20:10 +0000 | [diff] [blame] | 2127 | } |
| 2128 | IRDirty; |
| 2129 | |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 2130 | /* Pretty-print a dirty call */ |
sewardj | b3bce0e | 2004-09-14 23:20:10 +0000 | [diff] [blame] | 2131 | extern void ppIRDirty ( IRDirty* ); |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 2132 | |
| 2133 | /* Allocate an uninitialised dirty call */ |
sewardj | b3bce0e | 2004-09-14 23:20:10 +0000 | [diff] [blame] | 2134 | extern IRDirty* emptyIRDirty ( void ); |
| 2135 | |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 2136 | /* Deep-copy a dirty call */ |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 2137 | extern IRDirty* deepCopyIRDirty ( IRDirty* ); |
sewardj | 695cff9 | 2004-10-13 14:50:14 +0000 | [diff] [blame] | 2138 | |
sewardj | c5fc7aa | 2004-10-27 23:00:55 +0000 | [diff] [blame] | 2139 | /* A handy function which takes some of the tedium out of constructing |
| 2140 | dirty helper calls. The called function impliedly does not return |
sewardj | b8385d8 | 2004-11-02 01:34:15 +0000 | [diff] [blame] | 2141 | any value and has a constant-True guard. The call is marked as |
| 2142 | accessing neither guest state nor memory (hence the "unsafe" |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 2143 | designation) -- you can change this marking later if need be. A |
sewardj | b8385d8 | 2004-11-02 01:34:15 +0000 | [diff] [blame] | 2144 | suitable IRCallee is constructed from the supplied bits. */ |
sewardj | f965526 | 2004-10-31 20:02:16 +0000 | [diff] [blame] | 2145 | extern |
florian | 1ff4756 | 2012-10-21 02:09:51 +0000 | [diff] [blame] | 2146 | IRDirty* unsafeIRDirty_0_N ( Int regparms, const HChar* name, void* addr, |
sewardj | f965526 | 2004-10-31 20:02:16 +0000 | [diff] [blame] | 2147 | IRExpr** args ); |
sewardj | c5fc7aa | 2004-10-27 23:00:55 +0000 | [diff] [blame] | 2148 | |
| 2149 | /* Similarly, make a zero-annotation dirty call which returns a value, |
| 2150 | and assign that to the given temp. */ |
sewardj | f965526 | 2004-10-31 20:02:16 +0000 | [diff] [blame] | 2151 | extern |
| 2152 | IRDirty* unsafeIRDirty_1_N ( IRTemp dst, |
florian | 1ff4756 | 2012-10-21 02:09:51 +0000 | [diff] [blame] | 2153 | Int regparms, const HChar* name, void* addr, |
sewardj | f965526 | 2004-10-31 20:02:16 +0000 | [diff] [blame] | 2154 | IRExpr** args ); |
sewardj | c5fc7aa | 2004-10-27 23:00:55 +0000 | [diff] [blame] | 2155 | |
sewardj | b3bce0e | 2004-09-14 23:20:10 +0000 | [diff] [blame] | 2156 | |
sewardj | c4356f0 | 2007-11-09 21:15:04 +0000 | [diff] [blame] | 2157 | /* --------------- Memory Bus Events --------------- */ |
| 2158 | |
| 2159 | typedef |
| 2160 | enum { |
sewardj | cfe046e | 2013-01-17 14:23:53 +0000 | [diff] [blame] | 2161 | Imbe_Fence=0x1C00, |
sewardj | 6d615ba | 2011-09-26 16:19:43 +0000 | [diff] [blame] | 2162 | /* Needed only on ARM. It cancels a reservation made by a |
| 2163 | preceding Linked-Load, and needs to be handed through to the |
| 2164 | back end, just as LL and SC themselves are. */ |
| 2165 | Imbe_CancelReservation |
sewardj | c4356f0 | 2007-11-09 21:15:04 +0000 | [diff] [blame] | 2166 | } |
| 2167 | IRMBusEvent; |
| 2168 | |
| 2169 | extern void ppIRMBusEvent ( IRMBusEvent ); |
| 2170 | |
| 2171 | |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 2172 | /* --------------- Compare and Swap --------------- */ |
| 2173 | |
| 2174 | /* This denotes an atomic compare and swap operation, either |
| 2175 | a single-element one or a double-element one. |
| 2176 | |
| 2177 | In the single-element case: |
| 2178 | |
| 2179 | .addr is the memory address. |
| 2180 | .end is the endianness with which memory is accessed |
| 2181 | |
| 2182 | If .addr contains the same value as .expdLo, then .dataLo is |
| 2183 | written there, else there is no write. In both cases, the |
| 2184 | original value at .addr is copied into .oldLo. |
| 2185 | |
| 2186 | Types: .expdLo, .dataLo and .oldLo must all have the same type. |
| 2187 | It may be any integral type, viz: I8, I16, I32 or, for 64-bit |
| 2188 | guests, I64. |
| 2189 | |
| 2190 | .oldHi must be IRTemp_INVALID, and .expdHi and .dataHi must |
| 2191 | be NULL. |
| 2192 | |
| 2193 | In the double-element case: |
| 2194 | |
| 2195 | .addr is the memory address. |
| 2196 | .end is the endianness with which memory is accessed |
| 2197 | |
| 2198 | The operation is the same: |
| 2199 | |
| 2200 | If .addr contains the same value as .expdHi:.expdLo, then |
| 2201 | .dataHi:.dataLo is written there, else there is no write. In |
| 2202 | both cases the original value at .addr is copied into |
| 2203 | .oldHi:.oldLo. |
| 2204 | |
| 2205 | Types: .expdHi, .expdLo, .dataHi, .dataLo, .oldHi, .oldLo must |
| 2206 | all have the same type, which may be any integral type, viz: I8, |
| 2207 | I16, I32 or, for 64-bit guests, I64. |
| 2208 | |
| 2209 | The double-element case is complicated by the issue of |
| 2210 | endianness. In all cases, the two elements are understood to be |
| 2211 | located adjacently in memory, starting at the address .addr. |
| 2212 | |
| 2213 | If .end is Iend_LE, then the .xxxLo component is at the lower |
| 2214 | address and the .xxxHi component is at the higher address, and |
| 2215 | each component is itself stored little-endianly. |
| 2216 | |
| 2217 | If .end is Iend_BE, then the .xxxHi component is at the lower |
| 2218 | address and the .xxxLo component is at the higher address, and |
| 2219 | each component is itself stored big-endianly. |
| 2220 | |
| 2221 | This allows representing more cases than most architectures can |
| 2222 | handle. For example, x86 cannot do DCAS on 8- or 16-bit elements. |
| 2223 | |
| 2224 | How to know if the CAS succeeded? |
| 2225 | |
| 2226 | * if .oldLo == .expdLo (resp. .oldHi:.oldLo == .expdHi:.expdLo), |
| 2227 | then the CAS succeeded, .dataLo (resp. .dataHi:.dataLo) is now |
| 2228 | stored at .addr, and the original value there was .oldLo (resp |
| 2229 | .oldHi:.oldLo). |
| 2230 | |
| 2231 | * if .oldLo != .expdLo (resp. .oldHi:.oldLo != .expdHi:.expdLo), |
| 2232 | then the CAS failed, and the original value at .addr was .oldLo |
| 2233 | (resp. .oldHi:.oldLo). |
| 2234 | |
| 2235 | Hence it is easy to know whether or not the CAS succeeded. |
| 2236 | */ |
| 2237 | typedef |
| 2238 | struct { |
| 2239 | IRTemp oldHi; /* old value of *addr is written here */ |
| 2240 | IRTemp oldLo; |
| 2241 | IREndness end; /* endianness of the data in memory */ |
| 2242 | IRExpr* addr; /* store address */ |
| 2243 | IRExpr* expdHi; /* expected old value at *addr */ |
| 2244 | IRExpr* expdLo; |
| 2245 | IRExpr* dataHi; /* new value for *addr */ |
| 2246 | IRExpr* dataLo; |
| 2247 | } |
| 2248 | IRCAS; |
| 2249 | |
| 2250 | extern void ppIRCAS ( IRCAS* cas ); |
| 2251 | |
| 2252 | extern IRCAS* mkIRCAS ( IRTemp oldHi, IRTemp oldLo, |
| 2253 | IREndness end, IRExpr* addr, |
| 2254 | IRExpr* expdHi, IRExpr* expdLo, |
| 2255 | IRExpr* dataHi, IRExpr* dataLo ); |
| 2256 | |
| 2257 | extern IRCAS* deepCopyIRCAS ( IRCAS* ); |
| 2258 | |
florian | d6f38b3 | 2012-05-31 15:46:18 +0000 | [diff] [blame] | 2259 | |
| 2260 | /* ------------------ Circular Array Put ------------------ */ |
sewardj | cfe046e | 2013-01-17 14:23:53 +0000 | [diff] [blame] | 2261 | |
florian | d6f38b3 | 2012-05-31 15:46:18 +0000 | [diff] [blame] | 2262 | typedef |
| 2263 | struct { |
| 2264 | IRRegArray* descr; /* Part of guest state treated as circular */ |
| 2265 | IRExpr* ix; /* Variable part of index into array */ |
| 2266 | Int bias; /* Constant offset part of index into array */ |
| 2267 | IRExpr* data; /* The value to write */ |
| 2268 | } IRPutI; |
| 2269 | |
| 2270 | extern void ppIRPutI ( IRPutI* puti ); |
| 2271 | |
| 2272 | extern IRPutI* mkIRPutI ( IRRegArray* descr, IRExpr* ix, |
| 2273 | Int bias, IRExpr* data ); |
| 2274 | |
| 2275 | extern IRPutI* deepCopyIRPutI ( IRPutI* ); |
| 2276 | |
sewardj | c9069f2 | 2012-06-01 16:09:50 +0000 | [diff] [blame] | 2277 | |
sewardj | cfe046e | 2013-01-17 14:23:53 +0000 | [diff] [blame] | 2278 | /* --------------- Guarded loads and stores --------------- */ |
| 2279 | |
| 2280 | /* Conditional stores are straightforward. They are the same as |
| 2281 | normal stores, with an extra 'guard' field :: Ity_I1 that |
| 2282 | determines whether or not the store actually happens. If not, |
| 2283 | memory is unmodified. |
| 2284 | |
| 2285 | The semantics of this is that 'addr' and 'data' are fully evaluated |
| 2286 | even in the case where 'guard' evaluates to zero (false). |
| 2287 | */ |
| 2288 | typedef |
| 2289 | struct { |
| 2290 | IREndness end; /* Endianness of the store */ |
| 2291 | IRExpr* addr; /* store address */ |
| 2292 | IRExpr* data; /* value to write */ |
| 2293 | IRExpr* guard; /* Guarding value */ |
| 2294 | } |
| 2295 | IRStoreG; |
| 2296 | |
| 2297 | /* Conditional loads are a little more complex. 'addr' is the |
| 2298 | address, 'guard' is the guarding condition. If the load takes |
| 2299 | place, the loaded value is placed in 'dst'. If it does not take |
| 2300 | place, 'alt' is copied to 'dst'. However, the loaded value is not |
| 2301 | placed directly in 'dst' -- it is first subjected to the conversion |
| 2302 | specified by 'cvt'. |
| 2303 | |
| 2304 | For example, imagine doing a conditional 8-bit load, in which the |
| 2305 | loaded value is zero extended to 32 bits. Hence: |
| 2306 | * 'dst' and 'alt' must have type I32 |
| 2307 | * 'cvt' must be a unary op which converts I8 to I32. In this |
| 2308 | example, it would be ILGop_8Uto32. |
| 2309 | |
| 2310 | There is no explicit indication of the type at which the load is |
| 2311 | done, since that is inferrable from the arg type of 'cvt'. Note |
| 2312 | that the types of 'alt' and 'dst' and the result type of 'cvt' must |
| 2313 | all be the same. |
| 2314 | |
| 2315 | Semantically, 'addr' is evaluated even in the case where 'guard' |
| 2316 | evaluates to zero (false), and 'alt' is evaluated even when 'guard' |
| 2317 | evaluates to one (true). That is, 'addr' and 'alt' are always |
| 2318 | evaluated. |
| 2319 | */ |
| 2320 | typedef |
| 2321 | enum { |
| 2322 | ILGop_INVALID=0x1D00, |
| 2323 | ILGop_Ident32, /* 32 bit, no conversion */ |
| 2324 | ILGop_16Uto32, /* 16 bit load, Z-widen to 32 */ |
| 2325 | ILGop_16Sto32, /* 16 bit load, S-widen to 32 */ |
| 2326 | ILGop_8Uto32, /* 8 bit load, Z-widen to 32 */ |
| 2327 | ILGop_8Sto32 /* 8 bit load, S-widen to 32 */ |
| 2328 | } |
| 2329 | IRLoadGOp; |
| 2330 | |
| 2331 | typedef |
| 2332 | struct { |
| 2333 | IREndness end; /* Endianness of the load */ |
| 2334 | IRLoadGOp cvt; /* Conversion to apply to the loaded value */ |
| 2335 | IRTemp dst; /* Destination (LHS) of assignment */ |
| 2336 | IRExpr* addr; /* Address being loaded from */ |
| 2337 | IRExpr* alt; /* Value if load is not done. */ |
| 2338 | IRExpr* guard; /* Guarding value */ |
| 2339 | } |
| 2340 | IRLoadG; |
| 2341 | |
| 2342 | extern void ppIRStoreG ( IRStoreG* sg ); |
| 2343 | |
| 2344 | extern void ppIRLoadGOp ( IRLoadGOp cvt ); |
| 2345 | |
| 2346 | extern void ppIRLoadG ( IRLoadG* lg ); |
| 2347 | |
| 2348 | extern IRStoreG* mkIRStoreG ( IREndness end, |
| 2349 | IRExpr* addr, IRExpr* data, |
| 2350 | IRExpr* guard ); |
| 2351 | |
| 2352 | extern IRLoadG* mkIRLoadG ( IREndness end, IRLoadGOp cvt, |
| 2353 | IRTemp dst, IRExpr* addr, IRExpr* alt, |
| 2354 | IRExpr* guard ); |
| 2355 | |
| 2356 | |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 2357 | /* ------------------ Statements ------------------ */ |
sewardj | b3bce0e | 2004-09-14 23:20:10 +0000 | [diff] [blame] | 2358 | |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 2359 | /* The different kinds of statements. Their meaning is explained |
| 2360 | below in the comments for IRStmt. |
sewardj | 5a9ffab | 2005-05-12 17:55:01 +0000 | [diff] [blame] | 2361 | |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 2362 | Those marked META do not represent code, but rather extra |
| 2363 | information about the code. These statements can be removed |
| 2364 | without affecting the functional behaviour of the code, however |
| 2365 | they are required by some IR consumers such as tools that |
| 2366 | instrument the code. |
sewardj | 5a9ffab | 2005-05-12 17:55:01 +0000 | [diff] [blame] | 2367 | */ |
sewardj | c4356f0 | 2007-11-09 21:15:04 +0000 | [diff] [blame] | 2368 | |
sewardj | ac6b712 | 2004-06-27 01:03:57 +0000 | [diff] [blame] | 2369 | typedef |
sewardj | d2445f6 | 2005-03-21 00:15:53 +0000 | [diff] [blame] | 2370 | enum { |
sewardj | cfe046e | 2013-01-17 14:23:53 +0000 | [diff] [blame] | 2371 | Ist_NoOp=0x1E00, |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 2372 | Ist_IMark, /* META */ |
| 2373 | Ist_AbiHint, /* META */ |
| 2374 | Ist_Put, |
| 2375 | Ist_PutI, |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 2376 | Ist_WrTmp, |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 2377 | Ist_Store, |
sewardj | cfe046e | 2013-01-17 14:23:53 +0000 | [diff] [blame] | 2378 | Ist_LoadG, |
| 2379 | Ist_StoreG, |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 2380 | Ist_CAS, |
sewardj | e768e92 | 2009-11-26 17:17:37 +0000 | [diff] [blame] | 2381 | Ist_LLSC, |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 2382 | Ist_Dirty, |
sewardj | cfe046e | 2013-01-17 14:23:53 +0000 | [diff] [blame] | 2383 | Ist_MBE, |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 2384 | Ist_Exit |
sewardj | b3bce0e | 2004-09-14 23:20:10 +0000 | [diff] [blame] | 2385 | } |
sewardj | ac6b712 | 2004-06-27 01:03:57 +0000 | [diff] [blame] | 2386 | IRStmtTag; |
| 2387 | |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 2388 | /* A statement. Stored as a tagged union. 'tag' indicates what kind |
| 2389 | of expression this is. 'Ist' is the union that holds the fields. |
| 2390 | If an IRStmt 'st' has st.tag equal to Iex_Store, then it's a store |
| 2391 | statement, and the fields can be accessed with |
| 2392 | 'st.Ist.Store.<fieldname>'. |
| 2393 | |
| 2394 | For each kind of statement, we show what it looks like when |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 2395 | pretty-printed with ppIRStmt(). |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 2396 | */ |
sewardj | ac6b712 | 2004-06-27 01:03:57 +0000 | [diff] [blame] | 2397 | typedef |
| 2398 | struct _IRStmt { |
| 2399 | IRStmtTag tag; |
| 2400 | union { |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 2401 | /* A no-op (usually resulting from IR optimisation). Can be |
| 2402 | omitted without any effect. |
| 2403 | |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 2404 | ppIRStmt output: IR-NoOp |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 2405 | */ |
sewardj | ac6b712 | 2004-06-27 01:03:57 +0000 | [diff] [blame] | 2406 | struct { |
sewardj | d2445f6 | 2005-03-21 00:15:53 +0000 | [diff] [blame] | 2407 | } NoOp; |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 2408 | |
| 2409 | /* META: instruction mark. Marks the start of the statements |
| 2410 | that represent a single machine instruction (the end of |
| 2411 | those statements is marked by the next IMark or the end of |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 2412 | the IRSB). Contains the address and length of the |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 2413 | instruction. |
| 2414 | |
sewardj | 2f10aa6 | 2011-05-27 13:20:56 +0000 | [diff] [blame] | 2415 | It also contains a delta value. The delta must be |
| 2416 | subtracted from a guest program counter value before |
| 2417 | attempting to establish, by comparison with the address |
| 2418 | and length values, whether or not that program counter |
| 2419 | value refers to this instruction. For x86, amd64, ppc32, |
| 2420 | ppc64 and arm, the delta value is zero. For Thumb |
| 2421 | instructions, the delta value is one. This is because, on |
| 2422 | Thumb, guest PC values (guest_R15T) are encoded using the |
| 2423 | top 31 bits of the instruction address and a 1 in the lsb; |
| 2424 | hence they appear to be (numerically) 1 past the start of |
| 2425 | the instruction they refer to. IOW, guest_R15T on ARM |
| 2426 | holds a standard ARM interworking address. |
| 2427 | |
| 2428 | ppIRStmt output: ------ IMark(<addr>, <len>, <delta>) ------, |
| 2429 | eg. ------ IMark(0x4000792, 5, 0) ------, |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 2430 | */ |
sewardj | d2445f6 | 2005-03-21 00:15:53 +0000 | [diff] [blame] | 2431 | struct { |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 2432 | Addr64 addr; /* instruction address */ |
| 2433 | Int len; /* instruction length */ |
sewardj | 2f10aa6 | 2011-05-27 13:20:56 +0000 | [diff] [blame] | 2434 | UChar delta; /* addr = program counter as encoded in guest state |
| 2435 | - delta */ |
sewardj | f168931 | 2005-03-16 18:19:10 +0000 | [diff] [blame] | 2436 | } IMark; |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 2437 | |
| 2438 | /* META: An ABI hint, which says something about this |
| 2439 | platform's ABI. |
| 2440 | |
| 2441 | At the moment, the only AbiHint is one which indicates |
| 2442 | that a given chunk of address space, [base .. base+len-1], |
| 2443 | has become undefined. This is used on amd64-linux and |
| 2444 | some ppc variants to pass stack-redzoning hints to whoever |
sewardj | 478646f | 2008-05-01 20:13:04 +0000 | [diff] [blame] | 2445 | wants to see them. It also indicates the address of the |
| 2446 | next (dynamic) instruction that will be executed. This is |
| 2447 | to help Memcheck to origin tracking. |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 2448 | |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 2449 | ppIRStmt output: ====== AbiHint(<base>, <len>, <nia>) ====== |
sewardj | 478646f | 2008-05-01 20:13:04 +0000 | [diff] [blame] | 2450 | eg. ====== AbiHint(t1, 16, t2) ====== |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 2451 | */ |
sewardj | f168931 | 2005-03-16 18:19:10 +0000 | [diff] [blame] | 2452 | struct { |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 2453 | IRExpr* base; /* Start of undefined chunk */ |
| 2454 | Int len; /* Length of undefined chunk */ |
sewardj | 478646f | 2008-05-01 20:13:04 +0000 | [diff] [blame] | 2455 | IRExpr* nia; /* Address of next (guest) insn */ |
sewardj | 5a9ffab | 2005-05-12 17:55:01 +0000 | [diff] [blame] | 2456 | } AbiHint; |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 2457 | |
| 2458 | /* Write a guest register, at a fixed offset in the guest state. |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 2459 | ppIRStmt output: PUT(<offset>) = <data>, eg. PUT(60) = t1 |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 2460 | */ |
sewardj | 5a9ffab | 2005-05-12 17:55:01 +0000 | [diff] [blame] | 2461 | struct { |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 2462 | Int offset; /* Offset into the guest state */ |
| 2463 | IRExpr* data; /* The value to write */ |
sewardj | ac6b712 | 2004-06-27 01:03:57 +0000 | [diff] [blame] | 2464 | } Put; |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 2465 | |
| 2466 | /* Write a guest register, at a non-fixed offset in the guest |
| 2467 | state. See the comment for GetI expressions for more |
| 2468 | information. |
| 2469 | |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 2470 | ppIRStmt output: PUTI<descr>[<ix>,<bias>] = <data>, |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 2471 | eg. PUTI(64:8xF64)[t5,0] = t1 |
| 2472 | */ |
sewardj | ac6b712 | 2004-06-27 01:03:57 +0000 | [diff] [blame] | 2473 | struct { |
florian | d6f38b3 | 2012-05-31 15:46:18 +0000 | [diff] [blame] | 2474 | IRPutI* details; |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 2475 | } PutI; |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 2476 | |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 2477 | /* Assign a value to a temporary. Note that SSA rules require |
| 2478 | each tmp is only assigned to once. IR sanity checking will |
| 2479 | reject any block containing a temporary which is not assigned |
| 2480 | to exactly once. |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 2481 | |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 2482 | ppIRStmt output: t<tmp> = <data>, eg. t1 = 3 |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 2483 | */ |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 2484 | struct { |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 2485 | IRTemp tmp; /* Temporary (LHS of assignment) */ |
| 2486 | IRExpr* data; /* Expression (RHS of assignment) */ |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 2487 | } WrTmp; |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 2488 | |
sewardj | e768e92 | 2009-11-26 17:17:37 +0000 | [diff] [blame] | 2489 | /* Write a value to memory. This is a normal store, not a |
| 2490 | Store-Conditional. To represent a Store-Conditional, |
| 2491 | instead use IRStmt.LLSC. |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 2492 | ppIRStmt output: ST<end>(<addr>) = <data>, eg. STle(t1) = t2 |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 2493 | */ |
sewardj | ac6b712 | 2004-06-27 01:03:57 +0000 | [diff] [blame] | 2494 | struct { |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 2495 | IREndness end; /* Endianness of the store */ |
| 2496 | IRExpr* addr; /* store address */ |
| 2497 | IRExpr* data; /* value to write */ |
sewardj | af1ceca | 2005-06-30 23:31:27 +0000 | [diff] [blame] | 2498 | } Store; |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 2499 | |
sewardj | cfe046e | 2013-01-17 14:23:53 +0000 | [diff] [blame] | 2500 | /* Guarded store. Note that this is defined to evaluate all |
| 2501 | expression fields (addr, data) even if the guard evaluates |
| 2502 | to false. |
| 2503 | ppIRStmt output: |
| 2504 | if (<guard>) ST<end>(<addr>) = <data> */ |
| 2505 | struct { |
| 2506 | IRStoreG* details; |
| 2507 | } StoreG; |
| 2508 | |
| 2509 | /* Guarded load. Note that this is defined to evaluate all |
| 2510 | expression fields (addr, alt) even if the guard evaluates |
| 2511 | to false. |
| 2512 | ppIRStmt output: |
| 2513 | t<tmp> = if (<guard>) <cvt>(LD<end>(<addr>)) else <alt> */ |
| 2514 | struct { |
| 2515 | IRLoadG* details; |
| 2516 | } LoadG; |
| 2517 | |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 2518 | /* Do an atomic compare-and-swap operation. Semantics are |
| 2519 | described above on a comment at the definition of IRCAS. |
| 2520 | |
| 2521 | ppIRStmt output: |
| 2522 | t<tmp> = CAS<end>(<addr> :: <expected> -> <new>) |
| 2523 | eg |
| 2524 | t1 = CASle(t2 :: t3->Add32(t3,1)) |
| 2525 | which denotes a 32-bit atomic increment |
| 2526 | of a value at address t2 |
| 2527 | |
| 2528 | A double-element CAS may also be denoted, in which case <tmp>, |
| 2529 | <expected> and <new> are all pairs of items, separated by |
| 2530 | commas. |
| 2531 | */ |
| 2532 | struct { |
| 2533 | IRCAS* details; |
| 2534 | } CAS; |
| 2535 | |
sewardj | e768e92 | 2009-11-26 17:17:37 +0000 | [diff] [blame] | 2536 | /* Either Load-Linked or Store-Conditional, depending on |
| 2537 | STOREDATA. |
| 2538 | |
| 2539 | If STOREDATA is NULL then this is a Load-Linked, meaning |
| 2540 | that data is loaded from memory as normal, but a |
| 2541 | 'reservation' for the address is also lodged in the |
| 2542 | hardware. |
| 2543 | |
| 2544 | result = Load-Linked(addr, end) |
| 2545 | |
| 2546 | The data transfer type is the type of RESULT (I32, I64, |
| 2547 | etc). ppIRStmt output: |
| 2548 | |
| 2549 | result = LD<end>-Linked(<addr>), eg. LDbe-Linked(t1) |
| 2550 | |
| 2551 | If STOREDATA is not NULL then this is a Store-Conditional, |
| 2552 | hence: |
| 2553 | |
| 2554 | result = Store-Conditional(addr, storedata, end) |
| 2555 | |
| 2556 | The data transfer type is the type of STOREDATA and RESULT |
| 2557 | has type Ity_I1. The store may fail or succeed depending |
| 2558 | on the state of a previously lodged reservation on this |
| 2559 | address. RESULT is written 1 if the store succeeds and 0 |
| 2560 | if it fails. eg ppIRStmt output: |
| 2561 | |
| 2562 | result = ( ST<end>-Cond(<addr>) = <storedata> ) |
| 2563 | eg t3 = ( STbe-Cond(t1, t2) ) |
| 2564 | |
| 2565 | In all cases, the address must be naturally aligned for |
| 2566 | the transfer type -- any misaligned addresses should be |
| 2567 | caught by a dominating IR check and side exit. This |
| 2568 | alignment restriction exists because on at least some |
| 2569 | LL/SC platforms (ppc), stwcx. etc will trap w/ SIGBUS on |
| 2570 | misaligned addresses, and we have to actually generate |
| 2571 | stwcx. on the host, and we don't want it trapping on the |
| 2572 | host. |
| 2573 | |
| 2574 | Summary of rules for transfer type: |
| 2575 | STOREDATA == NULL (LL): |
| 2576 | transfer type = type of RESULT |
| 2577 | STOREDATA != NULL (SC): |
| 2578 | transfer type = type of STOREDATA, and RESULT :: Ity_I1 |
| 2579 | */ |
| 2580 | struct { |
| 2581 | IREndness end; |
| 2582 | IRTemp result; |
| 2583 | IRExpr* addr; |
| 2584 | IRExpr* storedata; /* NULL => LL, non-NULL => SC */ |
| 2585 | } LLSC; |
| 2586 | |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 2587 | /* Call (possibly conditionally) a C function that has side |
| 2588 | effects (ie. is "dirty"). See the comments above the |
| 2589 | IRDirty type declaration for more information. |
| 2590 | |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 2591 | ppIRStmt output: |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 2592 | t<tmp> = DIRTY <guard> <effects> |
| 2593 | ::: <callee>(<args>) |
| 2594 | eg. |
| 2595 | t1 = DIRTY t27 RdFX-gst(16,4) RdFX-gst(60,4) |
| 2596 | ::: foo{0x380035f4}(t2) |
| 2597 | */ |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 2598 | struct { |
sewardj | b3bce0e | 2004-09-14 23:20:10 +0000 | [diff] [blame] | 2599 | IRDirty* details; |
| 2600 | } Dirty; |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 2601 | |
sewardj | c4356f0 | 2007-11-09 21:15:04 +0000 | [diff] [blame] | 2602 | /* A memory bus event - a fence, or acquisition/release of the |
| 2603 | hardware bus lock. IR optimisation treats all these as fences |
| 2604 | across which no memory references may be moved. |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 2605 | ppIRStmt output: MBusEvent-Fence, |
sewardj | c4356f0 | 2007-11-09 21:15:04 +0000 | [diff] [blame] | 2606 | MBusEvent-BusLock, MBusEvent-BusUnlock. |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 2607 | */ |
sewardj | b3bce0e | 2004-09-14 23:20:10 +0000 | [diff] [blame] | 2608 | struct { |
sewardj | c4356f0 | 2007-11-09 21:15:04 +0000 | [diff] [blame] | 2609 | IRMBusEvent event; |
| 2610 | } MBE; |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 2611 | |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 2612 | /* Conditional exit from the middle of an IRSB. |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 2613 | ppIRStmt output: if (<guard>) goto {<jk>} <dst> |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 2614 | eg. if (t69) goto {Boring} 0x4000AAA:I32 |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 2615 | If <guard> is true, the guest state is also updated by |
| 2616 | PUT-ing <dst> at <offsIP>. This is done because a |
| 2617 | taken exit must update the guest program counter. |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 2618 | */ |
sewardj | 3e83893 | 2005-01-07 12:09:15 +0000 | [diff] [blame] | 2619 | struct { |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 2620 | IRExpr* guard; /* Conditional expression */ |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 2621 | IRConst* dst; /* Jump target (constant only) */ |
florian | d6f38b3 | 2012-05-31 15:46:18 +0000 | [diff] [blame] | 2622 | IRJumpKind jk; /* Jump kind */ |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 2623 | Int offsIP; /* Guest state offset for IP */ |
sewardj | 64e1d65 | 2004-07-12 14:00:46 +0000 | [diff] [blame] | 2624 | } Exit; |
sewardj | ac6b712 | 2004-06-27 01:03:57 +0000 | [diff] [blame] | 2625 | } Ist; |
sewardj | ac6b712 | 2004-06-27 01:03:57 +0000 | [diff] [blame] | 2626 | } |
| 2627 | IRStmt; |
sewardj | ec6ad59 | 2004-06-20 12:26:53 +0000 | [diff] [blame] | 2628 | |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 2629 | /* Statement constructors. */ |
sewardj | 5a9ffab | 2005-05-12 17:55:01 +0000 | [diff] [blame] | 2630 | extern IRStmt* IRStmt_NoOp ( void ); |
sewardj | 2f10aa6 | 2011-05-27 13:20:56 +0000 | [diff] [blame] | 2631 | extern IRStmt* IRStmt_IMark ( Addr64 addr, Int len, UChar delta ); |
sewardj | 478646f | 2008-05-01 20:13:04 +0000 | [diff] [blame] | 2632 | extern IRStmt* IRStmt_AbiHint ( IRExpr* base, Int len, IRExpr* nia ); |
sewardj | 5a9ffab | 2005-05-12 17:55:01 +0000 | [diff] [blame] | 2633 | extern IRStmt* IRStmt_Put ( Int off, IRExpr* data ); |
florian | d6f38b3 | 2012-05-31 15:46:18 +0000 | [diff] [blame] | 2634 | extern IRStmt* IRStmt_PutI ( IRPutI* details ); |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 2635 | extern IRStmt* IRStmt_WrTmp ( IRTemp tmp, IRExpr* data ); |
sewardj | e768e92 | 2009-11-26 17:17:37 +0000 | [diff] [blame] | 2636 | extern IRStmt* IRStmt_Store ( IREndness end, IRExpr* addr, IRExpr* data ); |
sewardj | cfe046e | 2013-01-17 14:23:53 +0000 | [diff] [blame] | 2637 | extern IRStmt* IRStmt_StoreG ( IREndness end, IRExpr* addr, IRExpr* data, |
| 2638 | IRExpr* guard ); |
| 2639 | extern IRStmt* IRStmt_LoadG ( IREndness end, IRLoadGOp cvt, IRTemp dst, |
| 2640 | IRExpr* addr, IRExpr* alt, IRExpr* guard ); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 2641 | extern IRStmt* IRStmt_CAS ( IRCAS* details ); |
sewardj | e768e92 | 2009-11-26 17:17:37 +0000 | [diff] [blame] | 2642 | extern IRStmt* IRStmt_LLSC ( IREndness end, IRTemp result, |
| 2643 | IRExpr* addr, IRExpr* storedata ); |
sewardj | 5a9ffab | 2005-05-12 17:55:01 +0000 | [diff] [blame] | 2644 | extern IRStmt* IRStmt_Dirty ( IRDirty* details ); |
sewardj | c4356f0 | 2007-11-09 21:15:04 +0000 | [diff] [blame] | 2645 | extern IRStmt* IRStmt_MBE ( IRMBusEvent event ); |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 2646 | extern IRStmt* IRStmt_Exit ( IRExpr* guard, IRJumpKind jk, IRConst* dst, |
| 2647 | Int offsIP ); |
sewardj | ec6ad59 | 2004-06-20 12:26:53 +0000 | [diff] [blame] | 2648 | |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 2649 | /* Deep-copy an IRStmt. */ |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 2650 | extern IRStmt* deepCopyIRStmt ( IRStmt* ); |
sewardj | 695cff9 | 2004-10-13 14:50:14 +0000 | [diff] [blame] | 2651 | |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 2652 | /* Pretty-print an IRStmt. */ |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 2653 | extern void ppIRStmt ( IRStmt* ); |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 2654 | |
| 2655 | |
sewardj | e539a40 | 2004-07-14 18:24:17 +0000 | [diff] [blame] | 2656 | /* ------------------ Basic Blocks ------------------ */ |
sewardj | 78c19df | 2004-07-12 22:49:27 +0000 | [diff] [blame] | 2657 | |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 2658 | /* Type environments: a bunch of statements, expressions, etc, are |
| 2659 | incomplete without an environment indicating the type of each |
| 2660 | IRTemp. So this provides one. IR temporaries are really just |
| 2661 | unsigned ints and so this provides an array, 0 .. n_types_used-1 of |
| 2662 | them. |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 2663 | */ |
| 2664 | typedef |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 2665 | struct { |
sewardj | e539a40 | 2004-07-14 18:24:17 +0000 | [diff] [blame] | 2666 | IRType* types; |
| 2667 | Int types_size; |
| 2668 | Int types_used; |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 2669 | } |
| 2670 | IRTypeEnv; |
| 2671 | |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 2672 | /* Obtain a new IRTemp */ |
| 2673 | extern IRTemp newIRTemp ( IRTypeEnv*, IRType ); |
| 2674 | |
| 2675 | /* Deep-copy a type environment */ |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 2676 | extern IRTypeEnv* deepCopyIRTypeEnv ( IRTypeEnv* ); |
sewardj | 695cff9 | 2004-10-13 14:50:14 +0000 | [diff] [blame] | 2677 | |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 2678 | /* Pretty-print a type environment */ |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 2679 | extern void ppIRTypeEnv ( IRTypeEnv* ); |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 2680 | |
sewardj | ec6ad59 | 2004-06-20 12:26:53 +0000 | [diff] [blame] | 2681 | |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 2682 | /* Code blocks, which in proper compiler terminology are superblocks |
| 2683 | (single entry, multiple exit code sequences) contain: |
| 2684 | |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 2685 | - A table giving a type for each temp (the "type environment") |
sewardj | d7cb853 | 2004-08-17 23:59:23 +0000 | [diff] [blame] | 2686 | - An expandable array of statements |
sewardj | e539a40 | 2004-07-14 18:24:17 +0000 | [diff] [blame] | 2687 | - An expression of type 32 or 64 bits, depending on the |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 2688 | guest's word size, indicating the next destination if the block |
| 2689 | executes all the way to the end, without a side exit |
sewardj | d7cb853 | 2004-08-17 23:59:23 +0000 | [diff] [blame] | 2690 | - An indication of any special actions (JumpKind) needed |
| 2691 | for this final jump. |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 2692 | - Offset of the IP field in the guest state. This will be |
| 2693 | updated before the final jump is done. |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 2694 | |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 2695 | "IRSB" stands for "IR Super Block". |
sewardj | ec6ad59 | 2004-06-20 12:26:53 +0000 | [diff] [blame] | 2696 | */ |
sewardj | ac6b712 | 2004-06-27 01:03:57 +0000 | [diff] [blame] | 2697 | typedef |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 2698 | struct { |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 2699 | IRTypeEnv* tyenv; |
sewardj | d7cb853 | 2004-08-17 23:59:23 +0000 | [diff] [blame] | 2700 | IRStmt** stmts; |
| 2701 | Int stmts_size; |
| 2702 | Int stmts_used; |
sewardj | e539a40 | 2004-07-14 18:24:17 +0000 | [diff] [blame] | 2703 | IRExpr* next; |
| 2704 | IRJumpKind jumpkind; |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 2705 | Int offsIP; |
sewardj | ac6b712 | 2004-06-27 01:03:57 +0000 | [diff] [blame] | 2706 | } |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 2707 | IRSB; |
sewardj | ec6ad59 | 2004-06-20 12:26:53 +0000 | [diff] [blame] | 2708 | |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 2709 | /* Allocate a new, uninitialised IRSB */ |
| 2710 | extern IRSB* emptyIRSB ( void ); |
sewardj | 695cff9 | 2004-10-13 14:50:14 +0000 | [diff] [blame] | 2711 | |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 2712 | /* Deep-copy an IRSB */ |
| 2713 | extern IRSB* deepCopyIRSB ( IRSB* ); |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 2714 | |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 2715 | /* Deep-copy an IRSB, except for the statements list, which set to be |
sewardj | 6f2f283 | 2006-11-24 23:32:55 +0000 | [diff] [blame] | 2716 | a new, empty, list of statements. */ |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 2717 | extern IRSB* deepCopyIRSBExceptStmts ( IRSB* ); |
sewardj | 57c10c8 | 2006-11-15 02:57:05 +0000 | [diff] [blame] | 2718 | |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 2719 | /* Pretty-print an IRSB */ |
| 2720 | extern void ppIRSB ( IRSB* ); |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 2721 | |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 2722 | /* Append an IRStmt to an IRSB */ |
| 2723 | extern void addStmtToIRSB ( IRSB*, IRStmt* ); |
sewardj | 695cff9 | 2004-10-13 14:50:14 +0000 | [diff] [blame] | 2724 | |
| 2725 | |
sewardj | ec6ad59 | 2004-06-20 12:26:53 +0000 | [diff] [blame] | 2726 | /*---------------------------------------------------------------*/ |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 2727 | /*--- Helper functions for the IR ---*/ |
sewardj | ec6ad59 | 2004-06-20 12:26:53 +0000 | [diff] [blame] | 2728 | /*---------------------------------------------------------------*/ |
| 2729 | |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 2730 | /* For messing with IR type environments */ |
sewardj | d7cb853 | 2004-08-17 23:59:23 +0000 | [diff] [blame] | 2731 | extern IRTypeEnv* emptyIRTypeEnv ( void ); |
sewardj | ec6ad59 | 2004-06-20 12:26:53 +0000 | [diff] [blame] | 2732 | |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 2733 | /* What is the type of this expression? */ |
sewardj | 6efd4a1 | 2004-07-15 03:54:23 +0000 | [diff] [blame] | 2734 | extern IRType typeOfIRConst ( IRConst* ); |
sewardj | 17442fe | 2004-09-20 14:54:28 +0000 | [diff] [blame] | 2735 | extern IRType typeOfIRTemp ( IRTypeEnv*, IRTemp ); |
sewardj | 6efd4a1 | 2004-07-15 03:54:23 +0000 | [diff] [blame] | 2736 | extern IRType typeOfIRExpr ( IRTypeEnv*, IRExpr* ); |
sewardj | ec6ad59 | 2004-06-20 12:26:53 +0000 | [diff] [blame] | 2737 | |
sewardj | cfe046e | 2013-01-17 14:23:53 +0000 | [diff] [blame] | 2738 | /* What are the arg and result type for this IRLoadGOp? */ |
| 2739 | extern void typeOfIRLoadGOp ( IRLoadGOp cvt, |
| 2740 | /*OUT*/IRType* t_res, |
| 2741 | /*OUT*/IRType* t_arg ); |
| 2742 | |
sewardj | 3543921 | 2004-07-14 22:36:10 +0000 | [diff] [blame] | 2743 | /* Sanity check a BB of IR */ |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 2744 | extern void sanityCheckIRSB ( IRSB* bb, |
florian | 1ff4756 | 2012-10-21 02:09:51 +0000 | [diff] [blame] | 2745 | const HChar* caller, |
sewardj | b923075 | 2004-12-29 19:25:06 +0000 | [diff] [blame] | 2746 | Bool require_flatness, |
| 2747 | IRType guest_word_size ); |
sewardj | cf78790 | 2004-11-03 09:08:33 +0000 | [diff] [blame] | 2748 | extern Bool isFlatIRStmt ( IRStmt* ); |
sewardj | ec6ad59 | 2004-06-20 12:26:53 +0000 | [diff] [blame] | 2749 | |
sewardj | 6d2638e | 2004-07-15 09:38:27 +0000 | [diff] [blame] | 2750 | /* Is this any value actually in the enumeration 'IRType' ? */ |
sewardj | 496a58d | 2005-03-20 18:44:44 +0000 | [diff] [blame] | 2751 | extern Bool isPlausibleIRType ( IRType ty ); |
sewardj | 6d2638e | 2004-07-15 09:38:27 +0000 | [diff] [blame] | 2752 | |
florian | 2245ce9 | 2012-08-28 16:49:30 +0000 | [diff] [blame] | 2753 | |
| 2754 | /*---------------------------------------------------------------*/ |
| 2755 | /*--- IR injection ---*/ |
| 2756 | /*---------------------------------------------------------------*/ |
| 2757 | void vex_inject_ir(IRSB *, IREndness); |
| 2758 | |
| 2759 | |
sewardj | 887a11a | 2004-07-05 17:26:47 +0000 | [diff] [blame] | 2760 | #endif /* ndef __LIBVEX_IR_H */ |
sewardj | ac9af02 | 2004-07-05 01:15:34 +0000 | [diff] [blame] | 2761 | |
| 2762 | |
| 2763 | /*---------------------------------------------------------------*/ |
sewardj | 887a11a | 2004-07-05 17:26:47 +0000 | [diff] [blame] | 2764 | /*--- libvex_ir.h ---*/ |
sewardj | ac9af02 | 2004-07-05 01:15:34 +0000 | [diff] [blame] | 2765 | /*---------------------------------------------------------------*/ |