sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 1 | |
| 2 | /*---------------------------------------------------------------*/ |
| 3 | /*--- begin host_arm64_defs.h ---*/ |
| 4 | /*---------------------------------------------------------------*/ |
| 5 | |
| 6 | /* |
| 7 | This file is part of Valgrind, a dynamic binary instrumentation |
| 8 | framework. |
| 9 | |
sewardj | 785952d | 2015-08-21 11:29:16 +0000 | [diff] [blame] | 10 | Copyright (C) 2013-2015 OpenWorks |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 11 | info@open-works.net |
| 12 | |
| 13 | This program is free software; you can redistribute it and/or |
| 14 | modify it under the terms of the GNU General Public License as |
| 15 | published by the Free Software Foundation; either version 2 of the |
| 16 | License, or (at your option) any later version. |
| 17 | |
| 18 | This program is distributed in the hope that it will be useful, but |
| 19 | WITHOUT ANY WARRANTY; without even the implied warranty of |
| 20 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 21 | General Public License for more details. |
| 22 | |
| 23 | You should have received a copy of the GNU General Public License |
| 24 | along with this program; if not, write to the Free Software |
| 25 | Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA |
| 26 | 02110-1301, USA. |
| 27 | |
| 28 | The GNU General Public License is contained in the file COPYING. |
| 29 | */ |
| 30 | |
| 31 | #ifndef __VEX_HOST_ARM64_DEFS_H |
| 32 | #define __VEX_HOST_ARM64_DEFS_H |
| 33 | |
| 34 | #include "libvex_basictypes.h" |
| 35 | #include "libvex.h" // VexArch |
| 36 | #include "host_generic_regs.h" // HReg |
| 37 | |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 38 | |
| 39 | /* --------- Registers. --------- */ |
| 40 | |
sewardj | a5b5022 | 2015-03-26 07:18:32 +0000 | [diff] [blame] | 41 | #define ST_IN static inline |
| 42 | ST_IN HReg hregARM64_X22 ( void ) { return mkHReg(False, HRcInt64, 22, 0); } |
| 43 | ST_IN HReg hregARM64_X23 ( void ) { return mkHReg(False, HRcInt64, 23, 1); } |
| 44 | ST_IN HReg hregARM64_X24 ( void ) { return mkHReg(False, HRcInt64, 24, 2); } |
| 45 | ST_IN HReg hregARM64_X25 ( void ) { return mkHReg(False, HRcInt64, 25, 3); } |
| 46 | ST_IN HReg hregARM64_X26 ( void ) { return mkHReg(False, HRcInt64, 26, 4); } |
| 47 | ST_IN HReg hregARM64_X27 ( void ) { return mkHReg(False, HRcInt64, 27, 5); } |
| 48 | ST_IN HReg hregARM64_X28 ( void ) { return mkHReg(False, HRcInt64, 28, 6); } |
| 49 | |
| 50 | ST_IN HReg hregARM64_X0 ( void ) { return mkHReg(False, HRcInt64, 0, 7); } |
| 51 | ST_IN HReg hregARM64_X1 ( void ) { return mkHReg(False, HRcInt64, 1, 8); } |
| 52 | ST_IN HReg hregARM64_X2 ( void ) { return mkHReg(False, HRcInt64, 2, 9); } |
| 53 | ST_IN HReg hregARM64_X3 ( void ) { return mkHReg(False, HRcInt64, 3, 10); } |
| 54 | ST_IN HReg hregARM64_X4 ( void ) { return mkHReg(False, HRcInt64, 4, 11); } |
| 55 | ST_IN HReg hregARM64_X5 ( void ) { return mkHReg(False, HRcInt64, 5, 12); } |
| 56 | ST_IN HReg hregARM64_X6 ( void ) { return mkHReg(False, HRcInt64, 6, 13); } |
| 57 | ST_IN HReg hregARM64_X7 ( void ) { return mkHReg(False, HRcInt64, 7, 14); } |
| 58 | |
| 59 | ST_IN HReg hregARM64_Q16 ( void ) { return mkHReg(False, HRcVec128, 16, 15); } |
| 60 | ST_IN HReg hregARM64_Q17 ( void ) { return mkHReg(False, HRcVec128, 17, 16); } |
| 61 | ST_IN HReg hregARM64_Q18 ( void ) { return mkHReg(False, HRcVec128, 18, 17); } |
| 62 | ST_IN HReg hregARM64_Q19 ( void ) { return mkHReg(False, HRcVec128, 19, 18); } |
| 63 | ST_IN HReg hregARM64_Q20 ( void ) { return mkHReg(False, HRcVec128, 20, 19); } |
| 64 | |
| 65 | ST_IN HReg hregARM64_D8 ( void ) { return mkHReg(False, HRcFlt64, 8, 20); } |
| 66 | ST_IN HReg hregARM64_D9 ( void ) { return mkHReg(False, HRcFlt64, 9, 21); } |
| 67 | ST_IN HReg hregARM64_D10 ( void ) { return mkHReg(False, HRcFlt64, 10, 22); } |
| 68 | ST_IN HReg hregARM64_D11 ( void ) { return mkHReg(False, HRcFlt64, 11, 23); } |
| 69 | ST_IN HReg hregARM64_D12 ( void ) { return mkHReg(False, HRcFlt64, 12, 24); } |
| 70 | ST_IN HReg hregARM64_D13 ( void ) { return mkHReg(False, HRcFlt64, 13, 25); } |
| 71 | |
| 72 | ST_IN HReg hregARM64_X8 ( void ) { return mkHReg(False, HRcInt64, 8, 26); } |
| 73 | ST_IN HReg hregARM64_X9 ( void ) { return mkHReg(False, HRcInt64, 9, 27); } |
| 74 | ST_IN HReg hregARM64_X21 ( void ) { return mkHReg(False, HRcInt64, 21, 28); } |
| 75 | #undef ST_IN |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 76 | |
| 77 | extern void ppHRegARM64 ( HReg ); |
| 78 | |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 79 | /* Number of registers used arg passing in function calls */ |
| 80 | #define ARM64_N_ARGREGS 8 /* x0 .. x7 */ |
| 81 | |
| 82 | |
| 83 | /* --------- Condition codes. --------- */ |
| 84 | |
| 85 | typedef |
| 86 | enum { |
| 87 | ARM64cc_EQ = 0, /* equal : Z=1 */ |
| 88 | ARM64cc_NE = 1, /* not equal : Z=0 */ |
| 89 | |
| 90 | ARM64cc_CS = 2, /* >=u (higher or same) : C=1 */ |
| 91 | ARM64cc_CC = 3, /* <u (lower) : C=0 */ |
| 92 | |
| 93 | ARM64cc_MI = 4, /* minus (negative) : N=1 */ |
| 94 | ARM64cc_PL = 5, /* plus (zero or +ve) : N=0 */ |
| 95 | |
| 96 | ARM64cc_VS = 6, /* overflow : V=1 */ |
| 97 | ARM64cc_VC = 7, /* no overflow : V=0 */ |
| 98 | |
| 99 | ARM64cc_HI = 8, /* >u (higher) : C=1 && Z=0 */ |
| 100 | ARM64cc_LS = 9, /* <=u (lower or same) : !(C=1 && Z=0) */ |
| 101 | |
| 102 | ARM64cc_GE = 10, /* >=s (signed greater or equal) : N=V */ |
| 103 | ARM64cc_LT = 11, /* <s (signed less than) : !(N=V) */ |
| 104 | |
| 105 | ARM64cc_GT = 12, /* >s (signed greater) : Z=0 && N=V */ |
| 106 | ARM64cc_LE = 13, /* <=s (signed less or equal) : !(Z=0 && N=V) */ |
| 107 | |
| 108 | ARM64cc_AL = 14, /* always (unconditional) */ |
| 109 | ARM64cc_NV = 15 /* in 64-bit mode also means "always" */ |
| 110 | } |
| 111 | ARM64CondCode; |
| 112 | |
| 113 | |
| 114 | /* --------- Memory address expressions (amodes). --------- */ |
| 115 | |
| 116 | typedef |
| 117 | enum { |
sewardj | 606c4ba | 2014-01-26 19:11:14 +0000 | [diff] [blame] | 118 | ARM64am_RI9=10, /* reg + simm9 */ |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 119 | ARM64am_RI12, /* reg + uimm12 * szB (iow, scaled by access size) */ |
| 120 | ARM64am_RR /* reg1 + reg2 */ |
| 121 | } |
| 122 | ARM64AModeTag; |
| 123 | |
| 124 | typedef |
| 125 | struct { |
| 126 | ARM64AModeTag tag; |
| 127 | union { |
| 128 | struct { |
| 129 | HReg reg; |
| 130 | Int simm9; /* -256 .. +255 */ |
| 131 | } RI9; |
| 132 | struct { |
| 133 | HReg reg; |
| 134 | UInt uimm12; /* 0 .. 4095 */ |
| 135 | UChar szB; /* 1, 2, 4, 8 (16 ?) */ |
| 136 | } RI12; |
| 137 | struct { |
| 138 | HReg base; |
| 139 | HReg index; |
| 140 | } RR; |
| 141 | } ARM64am; |
| 142 | } |
| 143 | ARM64AMode; |
| 144 | |
| 145 | extern ARM64AMode* ARM64AMode_RI9 ( HReg reg, Int simm9 ); |
| 146 | extern ARM64AMode* ARM64AMode_RI12 ( HReg reg, Int uimm12, UChar szB ); |
| 147 | extern ARM64AMode* ARM64AMode_RR ( HReg base, HReg index ); |
| 148 | |
| 149 | |
| 150 | /* --------- Reg or uimm12 or (uimm12 << 12) operands --------- */ |
| 151 | |
| 152 | typedef |
| 153 | enum { |
sewardj | 606c4ba | 2014-01-26 19:11:14 +0000 | [diff] [blame] | 154 | ARM64riA_I12=20, /* uimm12 << 0 or 12 only */ |
| 155 | ARM64riA_R /* reg */ |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 156 | } |
| 157 | ARM64RIATag; |
| 158 | |
| 159 | typedef |
| 160 | struct { |
| 161 | ARM64RIATag tag; |
| 162 | union { |
| 163 | struct { |
| 164 | UShort imm12; /* 0 .. 4095 */ |
| 165 | UChar shift; /* 0 or 12 only */ |
| 166 | } I12; |
| 167 | struct { |
| 168 | HReg reg; |
| 169 | } R; |
| 170 | } ARM64riA; |
| 171 | } |
| 172 | ARM64RIA; |
| 173 | |
| 174 | extern ARM64RIA* ARM64RIA_I12 ( UShort imm12, UChar shift ); |
| 175 | extern ARM64RIA* ARM64RIA_R ( HReg ); |
| 176 | |
| 177 | |
| 178 | /* --------- Reg or "bitfield" (logic immediate) operands --------- */ |
| 179 | |
| 180 | typedef |
| 181 | enum { |
| 182 | ARM64riL_I13=6, /* wierd-o bitfield immediate, 13 bits in total */ |
| 183 | ARM64riL_R /* reg */ |
| 184 | } |
| 185 | ARM64RILTag; |
| 186 | |
| 187 | typedef |
| 188 | struct { |
| 189 | ARM64RILTag tag; |
| 190 | union { |
| 191 | struct { |
| 192 | UChar bitN; /* 0 .. 1 */ |
| 193 | UChar immR; /* 0 .. 63 */ |
| 194 | UChar immS; /* 0 .. 63 */ |
| 195 | } I13; |
| 196 | struct { |
| 197 | HReg reg; |
| 198 | } R; |
| 199 | } ARM64riL; |
| 200 | } |
| 201 | ARM64RIL; |
| 202 | |
| 203 | extern ARM64RIL* ARM64RIL_I13 ( UChar bitN, UChar immR, UChar immS ); |
| 204 | extern ARM64RIL* ARM64RIL_R ( HReg ); |
| 205 | |
| 206 | |
| 207 | /* --------------- Reg or uimm6 operands --------------- */ |
| 208 | |
| 209 | typedef |
| 210 | enum { |
sewardj | 606c4ba | 2014-01-26 19:11:14 +0000 | [diff] [blame] | 211 | ARM64ri6_I6=30, /* uimm6, 1 .. 63 only */ |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 212 | ARM64ri6_R /* reg */ |
| 213 | } |
| 214 | ARM64RI6Tag; |
| 215 | |
| 216 | typedef |
| 217 | struct { |
| 218 | ARM64RI6Tag tag; |
| 219 | union { |
| 220 | struct { |
| 221 | UInt imm6; /* 1 .. 63 */ |
| 222 | } I6; |
| 223 | struct { |
| 224 | HReg reg; |
| 225 | } R; |
| 226 | } ARM64ri6; |
| 227 | } |
| 228 | ARM64RI6; |
| 229 | |
| 230 | extern ARM64RI6* ARM64RI6_I6 ( UInt imm6 ); |
| 231 | extern ARM64RI6* ARM64RI6_R ( HReg ); |
| 232 | |
| 233 | |
| 234 | /* --------------------- Instructions --------------------- */ |
| 235 | |
| 236 | typedef |
| 237 | enum { |
sewardj | 606c4ba | 2014-01-26 19:11:14 +0000 | [diff] [blame] | 238 | ARM64lo_AND=40, |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 239 | ARM64lo_OR, |
| 240 | ARM64lo_XOR |
| 241 | } |
| 242 | ARM64LogicOp; |
| 243 | |
| 244 | typedef |
| 245 | enum { |
sewardj | 606c4ba | 2014-01-26 19:11:14 +0000 | [diff] [blame] | 246 | ARM64sh_SHL=50, |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 247 | ARM64sh_SHR, |
| 248 | ARM64sh_SAR |
| 249 | } |
| 250 | ARM64ShiftOp; |
| 251 | |
| 252 | typedef |
| 253 | enum { |
sewardj | 606c4ba | 2014-01-26 19:11:14 +0000 | [diff] [blame] | 254 | ARM64un_NEG=60, |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 255 | ARM64un_NOT, |
| 256 | ARM64un_CLZ, |
| 257 | } |
| 258 | ARM64UnaryOp; |
| 259 | |
| 260 | typedef |
| 261 | enum { |
sewardj | 606c4ba | 2014-01-26 19:11:14 +0000 | [diff] [blame] | 262 | ARM64mul_PLAIN=70, /* lo64(64 * 64) */ |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 263 | ARM64mul_ZX, /* hi64(64 *u 64) */ |
| 264 | ARM64mul_SX /* hi64(64 *s 64) */ |
| 265 | } |
| 266 | ARM64MulOp; |
| 267 | |
| 268 | typedef |
| 269 | /* These characterise an integer-FP conversion, but don't imply any |
| 270 | particular direction. */ |
| 271 | enum { |
sewardj | 606c4ba | 2014-01-26 19:11:14 +0000 | [diff] [blame] | 272 | ARM64cvt_F32_I32S=80, |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 273 | ARM64cvt_F64_I32S, |
| 274 | ARM64cvt_F32_I64S, |
| 275 | ARM64cvt_F64_I64S, |
| 276 | ARM64cvt_F32_I32U, |
| 277 | ARM64cvt_F64_I32U, |
| 278 | ARM64cvt_F32_I64U, |
| 279 | ARM64cvt_F64_I64U, |
| 280 | ARM64cvt_INVALID |
| 281 | } |
| 282 | ARM64CvtOp; |
| 283 | |
| 284 | typedef |
| 285 | enum { |
sewardj | 606c4ba | 2014-01-26 19:11:14 +0000 | [diff] [blame] | 286 | ARM64fpb_ADD=100, |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 287 | ARM64fpb_SUB, |
| 288 | ARM64fpb_MUL, |
| 289 | ARM64fpb_DIV, |
| 290 | ARM64fpb_INVALID |
| 291 | } |
| 292 | ARM64FpBinOp; |
| 293 | |
| 294 | typedef |
| 295 | enum { |
sewardj | 606c4ba | 2014-01-26 19:11:14 +0000 | [diff] [blame] | 296 | ARM64fpu_NEG=110, |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 297 | ARM64fpu_ABS, |
| 298 | ARM64fpu_SQRT, |
| 299 | ARM64fpu_RINT, |
sewardj | 89cefe4 | 2015-02-24 12:21:01 +0000 | [diff] [blame] | 300 | ARM64fpu_RECPX, |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 301 | ARM64fpu_INVALID |
| 302 | } |
| 303 | ARM64FpUnaryOp; |
| 304 | |
sewardj | 606c4ba | 2014-01-26 19:11:14 +0000 | [diff] [blame] | 305 | typedef |
| 306 | enum { |
sewardj | 25523c4 | 2014-06-15 19:36:29 +0000 | [diff] [blame] | 307 | ARM64vecb_ADD64x2=120, ARM64vecb_ADD32x4, |
| 308 | ARM64vecb_ADD16x8, ARM64vecb_ADD8x16, |
| 309 | ARM64vecb_SUB64x2, ARM64vecb_SUB32x4, |
| 310 | ARM64vecb_SUB16x8, ARM64vecb_SUB8x16, |
| 311 | ARM64vecb_MUL32x4, |
| 312 | ARM64vecb_MUL16x8, ARM64vecb_MUL8x16, |
| 313 | ARM64vecb_FADD64x2, ARM64vecb_FADD32x4, |
| 314 | ARM64vecb_FSUB64x2, ARM64vecb_FSUB32x4, |
| 315 | ARM64vecb_FMUL64x2, ARM64vecb_FMUL32x4, |
| 316 | ARM64vecb_FDIV64x2, ARM64vecb_FDIV32x4, |
sewardj | 76927e6 | 2014-11-17 11:21:21 +0000 | [diff] [blame] | 317 | ARM64vecb_FMAX64x2, ARM64vecb_FMAX32x4, |
| 318 | ARM64vecb_FMIN64x2, ARM64vecb_FMIN32x4, |
sewardj | 25523c4 | 2014-06-15 19:36:29 +0000 | [diff] [blame] | 319 | ARM64vecb_UMAX32x4, |
| 320 | ARM64vecb_UMAX16x8, ARM64vecb_UMAX8x16, |
| 321 | ARM64vecb_UMIN32x4, |
| 322 | ARM64vecb_UMIN16x8, ARM64vecb_UMIN8x16, |
| 323 | ARM64vecb_SMAX32x4, |
| 324 | ARM64vecb_SMAX16x8, ARM64vecb_SMAX8x16, |
| 325 | ARM64vecb_SMIN32x4, |
| 326 | ARM64vecb_SMIN16x8, ARM64vecb_SMIN8x16, |
sewardj | ecde697 | 2014-02-05 11:01:19 +0000 | [diff] [blame] | 327 | ARM64vecb_AND, |
| 328 | ARM64vecb_ORR, |
sewardj | e520bb3 | 2014-02-17 11:00:53 +0000 | [diff] [blame] | 329 | ARM64vecb_XOR, |
sewardj | 25523c4 | 2014-06-15 19:36:29 +0000 | [diff] [blame] | 330 | ARM64vecb_CMEQ64x2, ARM64vecb_CMEQ32x4, |
| 331 | ARM64vecb_CMEQ16x8, ARM64vecb_CMEQ8x16, |
| 332 | ARM64vecb_CMHI64x2, ARM64vecb_CMHI32x4, /* >u */ |
| 333 | ARM64vecb_CMHI16x8, ARM64vecb_CMHI8x16, |
| 334 | ARM64vecb_CMGT64x2, ARM64vecb_CMGT32x4, /* >s */ |
| 335 | ARM64vecb_CMGT16x8, ARM64vecb_CMGT8x16, |
| 336 | ARM64vecb_FCMEQ64x2, ARM64vecb_FCMEQ32x4, |
| 337 | ARM64vecb_FCMGE64x2, ARM64vecb_FCMGE32x4, |
| 338 | ARM64vecb_FCMGT64x2, ARM64vecb_FCMGT32x4, |
sewardj | 92d0ae3 | 2014-04-03 13:48:54 +0000 | [diff] [blame] | 339 | ARM64vecb_TBL1, |
sewardj | 25523c4 | 2014-06-15 19:36:29 +0000 | [diff] [blame] | 340 | ARM64vecb_UZP164x2, ARM64vecb_UZP132x4, |
| 341 | ARM64vecb_UZP116x8, ARM64vecb_UZP18x16, |
| 342 | ARM64vecb_UZP264x2, ARM64vecb_UZP232x4, |
| 343 | ARM64vecb_UZP216x8, ARM64vecb_UZP28x16, |
| 344 | ARM64vecb_ZIP132x4, ARM64vecb_ZIP116x8, |
| 345 | ARM64vecb_ZIP18x16, ARM64vecb_ZIP232x4, |
| 346 | ARM64vecb_ZIP216x8, ARM64vecb_ZIP28x16, |
sewardj | 168c8bd | 2014-06-25 13:05:23 +0000 | [diff] [blame] | 347 | ARM64vecb_PMUL8x16, |
sewardj | 31b5a95 | 2014-06-26 07:41:14 +0000 | [diff] [blame] | 348 | ARM64vecb_PMULL8x8, |
sewardj | 6f312d0 | 2014-06-28 12:21:37 +0000 | [diff] [blame] | 349 | ARM64vecb_UMULL2DSS, |
| 350 | ARM64vecb_UMULL4SHH, ARM64vecb_UMULL8HBB, |
| 351 | ARM64vecb_SMULL2DSS, |
| 352 | ARM64vecb_SMULL4SHH, ARM64vecb_SMULL8HBB, |
sewardj | 51d012a | 2014-07-21 09:19:50 +0000 | [diff] [blame] | 353 | ARM64vecb_SQADD64x2, ARM64vecb_SQADD32x4, |
| 354 | ARM64vecb_SQADD16x8, ARM64vecb_SQADD8x16, |
| 355 | ARM64vecb_UQADD64x2, ARM64vecb_UQADD32x4, |
| 356 | ARM64vecb_UQADD16x8, ARM64vecb_UQADD8x16, |
| 357 | ARM64vecb_SQSUB64x2, ARM64vecb_SQSUB32x4, |
| 358 | ARM64vecb_SQSUB16x8, ARM64vecb_SQSUB8x16, |
| 359 | ARM64vecb_UQSUB64x2, ARM64vecb_UQSUB32x4, |
| 360 | ARM64vecb_UQSUB16x8, ARM64vecb_UQSUB8x16, |
| 361 | ARM64vecb_SQDMULL2DSS, |
| 362 | ARM64vecb_SQDMULL4SHH, |
sewardj | 54ffa1d | 2014-07-22 09:27:49 +0000 | [diff] [blame] | 363 | ARM64vecb_SQDMULH32x4, |
| 364 | ARM64vecb_SQDMULH16x8, |
| 365 | ARM64vecb_SQRDMULH32x4, |
| 366 | ARM64vecb_SQRDMULH16x8, |
sewardj | 1297218 | 2014-08-04 08:09:47 +0000 | [diff] [blame] | 367 | ARM64vecb_SQSHL64x2, ARM64vecb_SQSHL32x4, |
| 368 | ARM64vecb_SQSHL16x8, ARM64vecb_SQSHL8x16, |
| 369 | ARM64vecb_UQSHL64x2, ARM64vecb_UQSHL32x4, |
| 370 | ARM64vecb_UQSHL16x8, ARM64vecb_UQSHL8x16, |
| 371 | ARM64vecb_SQRSHL64x2, ARM64vecb_SQRSHL32x4, |
| 372 | ARM64vecb_SQRSHL16x8, ARM64vecb_SQRSHL8x16, |
| 373 | ARM64vecb_UQRSHL64x2, ARM64vecb_UQRSHL32x4, |
| 374 | ARM64vecb_UQRSHL16x8, ARM64vecb_UQRSHL8x16, |
sewardj | a6b61f0 | 2014-08-17 18:32:14 +0000 | [diff] [blame] | 375 | ARM64vecb_SSHL64x2, ARM64vecb_SSHL32x4, |
| 376 | ARM64vecb_SSHL16x8, ARM64vecb_SSHL8x16, |
| 377 | ARM64vecb_USHL64x2, ARM64vecb_USHL32x4, |
| 378 | ARM64vecb_USHL16x8, ARM64vecb_USHL8x16, |
| 379 | ARM64vecb_SRSHL64x2, ARM64vecb_SRSHL32x4, |
| 380 | ARM64vecb_SRSHL16x8, ARM64vecb_SRSHL8x16, |
| 381 | ARM64vecb_URSHL64x2, ARM64vecb_URSHL32x4, |
| 382 | ARM64vecb_URSHL16x8, ARM64vecb_URSHL8x16, |
sewardj | 89cefe4 | 2015-02-24 12:21:01 +0000 | [diff] [blame] | 383 | ARM64vecb_FRECPS64x2, ARM64vecb_FRECPS32x4, |
| 384 | ARM64vecb_FRSQRTS64x2, ARM64vecb_FRSQRTS32x4, |
sewardj | 606c4ba | 2014-01-26 19:11:14 +0000 | [diff] [blame] | 385 | ARM64vecb_INVALID |
| 386 | } |
| 387 | ARM64VecBinOp; |
| 388 | |
sewardj | fab0914 | 2014-02-10 10:28:13 +0000 | [diff] [blame] | 389 | typedef |
| 390 | enum { |
sewardj | fc261d9 | 2014-08-24 20:36:14 +0000 | [diff] [blame] | 391 | ARM64vecmo_SUQADD64x2=300, ARM64vecmo_SUQADD32x4, |
sewardj | f7003bc | 2014-08-18 12:28:02 +0000 | [diff] [blame] | 392 | ARM64vecmo_SUQADD16x8, ARM64vecmo_SUQADD8x16, |
| 393 | ARM64vecmo_USQADD64x2, ARM64vecmo_USQADD32x4, |
| 394 | ARM64vecmo_USQADD16x8, ARM64vecmo_USQADD8x16, |
| 395 | ARM64vecmo_INVALID |
| 396 | } |
| 397 | ARM64VecModifyOp; |
| 398 | |
| 399 | typedef |
| 400 | enum { |
sewardj | fc261d9 | 2014-08-24 20:36:14 +0000 | [diff] [blame] | 401 | ARM64vecu_FNEG64x2=350, ARM64vecu_FNEG32x4, |
sewardj | 25523c4 | 2014-06-15 19:36:29 +0000 | [diff] [blame] | 402 | ARM64vecu_FABS64x2, ARM64vecu_FABS32x4, |
sewardj | e520bb3 | 2014-02-17 11:00:53 +0000 | [diff] [blame] | 403 | ARM64vecu_NOT, |
sewardj | 25523c4 | 2014-06-15 19:36:29 +0000 | [diff] [blame] | 404 | ARM64vecu_ABS64x2, ARM64vecu_ABS32x4, |
| 405 | ARM64vecu_ABS16x8, ARM64vecu_ABS8x16, |
sewardj | 2b6fd5e | 2014-06-19 14:21:37 +0000 | [diff] [blame] | 406 | ARM64vecu_CLS32x4, ARM64vecu_CLS16x8, ARM64vecu_CLS8x16, |
| 407 | ARM64vecu_CLZ32x4, ARM64vecu_CLZ16x8, ARM64vecu_CLZ8x16, |
| 408 | ARM64vecu_CNT8x16, |
sewardj | 715d162 | 2014-06-26 12:39:05 +0000 | [diff] [blame] | 409 | ARM64vecu_RBIT, |
| 410 | ARM64vecu_REV1616B, |
sewardj | df9d6d5 | 2014-06-27 10:43:22 +0000 | [diff] [blame] | 411 | ARM64vecu_REV3216B, ARM64vecu_REV328H, |
| 412 | ARM64vecu_REV6416B, ARM64vecu_REV648H, ARM64vecu_REV644S, |
sewardj | fc261d9 | 2014-08-24 20:36:14 +0000 | [diff] [blame] | 413 | ARM64vecu_URECPE32x4, |
| 414 | ARM64vecu_URSQRTE32x4, |
sewardj | 89cefe4 | 2015-02-24 12:21:01 +0000 | [diff] [blame] | 415 | ARM64vecu_FRECPE64x2, ARM64vecu_FRECPE32x4, |
| 416 | ARM64vecu_FRSQRTE64x2, ARM64vecu_FRSQRTE32x4, |
sewardj | 4b21c3d | 2015-04-06 19:34:03 +0000 | [diff] [blame] | 417 | ARM64vecu_FSQRT64x2, ARM64vecu_FSQRT32x4, |
sewardj | fab0914 | 2014-02-10 10:28:13 +0000 | [diff] [blame] | 418 | ARM64vecu_INVALID |
| 419 | } |
| 420 | ARM64VecUnaryOp; |
| 421 | |
sewardj | e520bb3 | 2014-02-17 11:00:53 +0000 | [diff] [blame] | 422 | typedef |
| 423 | enum { |
sewardj | fc261d9 | 2014-08-24 20:36:14 +0000 | [diff] [blame] | 424 | ARM64vecshi_USHR64x2=400, ARM64vecshi_USHR32x4, |
sewardj | a6b61f0 | 2014-08-17 18:32:14 +0000 | [diff] [blame] | 425 | ARM64vecshi_USHR16x8, ARM64vecshi_USHR8x16, |
| 426 | ARM64vecshi_SSHR64x2, ARM64vecshi_SSHR32x4, |
| 427 | ARM64vecshi_SSHR16x8, ARM64vecshi_SSHR8x16, |
| 428 | ARM64vecshi_SHL64x2, ARM64vecshi_SHL32x4, |
| 429 | ARM64vecshi_SHL16x8, ARM64vecshi_SHL8x16, |
sewardj | ecedd98 | 2014-08-11 14:02:47 +0000 | [diff] [blame] | 430 | /* These narrowing shifts zero out the top half of the destination |
| 431 | register. */ |
sewardj | a6b61f0 | 2014-08-17 18:32:14 +0000 | [diff] [blame] | 432 | ARM64vecshi_SQSHRN2SD, ARM64vecshi_SQSHRN4HS, ARM64vecshi_SQSHRN8BH, |
| 433 | ARM64vecshi_UQSHRN2SD, ARM64vecshi_UQSHRN4HS, ARM64vecshi_UQSHRN8BH, |
| 434 | ARM64vecshi_SQSHRUN2SD, ARM64vecshi_SQSHRUN4HS, ARM64vecshi_SQSHRUN8BH, |
| 435 | ARM64vecshi_SQRSHRN2SD, ARM64vecshi_SQRSHRN4HS, ARM64vecshi_SQRSHRN8BH, |
| 436 | ARM64vecshi_UQRSHRN2SD, ARM64vecshi_UQRSHRN4HS, ARM64vecshi_UQRSHRN8BH, |
| 437 | ARM64vecshi_SQRSHRUN2SD, ARM64vecshi_SQRSHRUN4HS, ARM64vecshi_SQRSHRUN8BH, |
sewardj | a97dddf | 2014-08-14 22:26:52 +0000 | [diff] [blame] | 438 | /* Saturating left shifts, of various flavours. */ |
sewardj | a6b61f0 | 2014-08-17 18:32:14 +0000 | [diff] [blame] | 439 | ARM64vecshi_UQSHL64x2, ARM64vecshi_UQSHL32x4, |
| 440 | ARM64vecshi_UQSHL16x8, ARM64vecshi_UQSHL8x16, |
| 441 | ARM64vecshi_SQSHL64x2, ARM64vecshi_SQSHL32x4, |
| 442 | ARM64vecshi_SQSHL16x8, ARM64vecshi_SQSHL8x16, |
| 443 | ARM64vecshi_SQSHLU64x2, ARM64vecshi_SQSHLU32x4, |
| 444 | ARM64vecshi_SQSHLU16x8, ARM64vecshi_SQSHLU8x16, |
| 445 | ARM64vecshi_INVALID |
sewardj | e520bb3 | 2014-02-17 11:00:53 +0000 | [diff] [blame] | 446 | } |
sewardj | a6b61f0 | 2014-08-17 18:32:14 +0000 | [diff] [blame] | 447 | ARM64VecShiftImmOp; |
sewardj | e520bb3 | 2014-02-17 11:00:53 +0000 | [diff] [blame] | 448 | |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 449 | typedef |
| 450 | enum { |
sewardj | fc261d9 | 2014-08-24 20:36:14 +0000 | [diff] [blame] | 451 | ARM64vecna_XTN=450, |
sewardj | ecedd98 | 2014-08-11 14:02:47 +0000 | [diff] [blame] | 452 | ARM64vecna_SQXTN, |
| 453 | ARM64vecna_UQXTN, |
| 454 | ARM64vecna_SQXTUN, |
| 455 | ARM64vecna_INVALID |
| 456 | } |
| 457 | ARM64VecNarrowOp; |
| 458 | |
| 459 | typedef |
| 460 | enum { |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 461 | /* baseline */ |
| 462 | ARM64in_Arith=1220, |
| 463 | ARM64in_Cmp, |
| 464 | ARM64in_Logic, |
| 465 | ARM64in_Test, |
| 466 | ARM64in_Shift, |
| 467 | ARM64in_Unary, |
| 468 | ARM64in_MovI, /* int reg-reg move */ |
| 469 | ARM64in_Imm64, |
| 470 | ARM64in_LdSt64, |
| 471 | ARM64in_LdSt32, /* w/ ZX loads */ |
| 472 | ARM64in_LdSt16, /* w/ ZX loads */ |
| 473 | ARM64in_LdSt8, /* w/ ZX loads */ |
| 474 | ARM64in_XDirect, /* direct transfer to GA */ |
| 475 | ARM64in_XIndir, /* indirect transfer to GA */ |
| 476 | ARM64in_XAssisted, /* assisted transfer to GA */ |
| 477 | ARM64in_CSel, |
| 478 | ARM64in_Call, |
| 479 | ARM64in_AddToSP, /* move SP by small, signed constant */ |
| 480 | ARM64in_FromSP, /* move SP to integer register */ |
| 481 | ARM64in_Mul, |
sewardj | 7d00913 | 2014-02-20 17:43:38 +0000 | [diff] [blame] | 482 | ARM64in_LdrEX, |
| 483 | ARM64in_StrEX, |
| 484 | ARM64in_MFence, |
Elliott Hughes | a0664b9 | 2017-04-18 17:46:52 -0700 | [diff] [blame] | 485 | ARM64in_ClrEX, |
sewardj | 606c4ba | 2014-01-26 19:11:14 +0000 | [diff] [blame] | 486 | /* ARM64in_V*: scalar ops involving vector registers */ |
sewardj | 400d6b9 | 2015-03-30 09:01:51 +0000 | [diff] [blame] | 487 | ARM64in_VLdStH, /* ld/st to/from low 16 bits of vec reg, imm offset */ |
| 488 | ARM64in_VLdStS, /* ld/st to/from low 32 bits of vec reg, imm offset */ |
| 489 | ARM64in_VLdStD, /* ld/st to/from low 64 bits of vec reg, imm offset */ |
| 490 | ARM64in_VLdStQ, /* ld/st to/from all 128 bits of vec reg, no offset */ |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 491 | ARM64in_VCvtI2F, |
| 492 | ARM64in_VCvtF2I, |
sewardj | 400d6b9 | 2015-03-30 09:01:51 +0000 | [diff] [blame] | 493 | ARM64in_VCvtSD, /* scalar 32 bit FP <--> 64 bit FP */ |
| 494 | ARM64in_VCvtHS, /* scalar 16 bit FP <--> 32 bit FP */ |
| 495 | ARM64in_VCvtHD, /* scalar 16 bit FP <--> 64 bit FP */ |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 496 | ARM64in_VUnaryD, |
| 497 | ARM64in_VUnaryS, |
| 498 | ARM64in_VBinD, |
| 499 | ARM64in_VBinS, |
| 500 | ARM64in_VCmpD, |
| 501 | ARM64in_VCmpS, |
sewardj | e23ec11 | 2014-11-15 16:07:14 +0000 | [diff] [blame] | 502 | ARM64in_VFCSel, |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 503 | ARM64in_FPCR, |
sewardj | 1297218 | 2014-08-04 08:09:47 +0000 | [diff] [blame] | 504 | ARM64in_FPSR, |
sewardj | 606c4ba | 2014-01-26 19:11:14 +0000 | [diff] [blame] | 505 | /* ARM64in_V*V: vector ops on vector registers */ |
| 506 | ARM64in_VBinV, |
sewardj | f7003bc | 2014-08-18 12:28:02 +0000 | [diff] [blame] | 507 | ARM64in_VModifyV, |
sewardj | fab0914 | 2014-02-10 10:28:13 +0000 | [diff] [blame] | 508 | ARM64in_VUnaryV, |
sewardj | 606c4ba | 2014-01-26 19:11:14 +0000 | [diff] [blame] | 509 | ARM64in_VNarrowV, |
sewardj | e520bb3 | 2014-02-17 11:00:53 +0000 | [diff] [blame] | 510 | ARM64in_VShiftImmV, |
sewardj | ab33a7a | 2014-06-19 22:20:47 +0000 | [diff] [blame] | 511 | ARM64in_VExtV, |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 512 | ARM64in_VImmQ, |
| 513 | ARM64in_VDfromX, /* Move an Xreg to a Dreg */ |
sewardj | 1297218 | 2014-08-04 08:09:47 +0000 | [diff] [blame] | 514 | ARM64in_VQfromX, /* Move an Xreg to a Qreg lo64, and zero hi64 */ |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 515 | ARM64in_VQfromXX, /* Move 2 Xregs to a Qreg */ |
| 516 | ARM64in_VXfromQ, /* Move half a Qreg to an Xreg */ |
sewardj | 85fbb02 | 2014-06-12 13:16:01 +0000 | [diff] [blame] | 517 | ARM64in_VXfromDorS, /* Move Dreg or Sreg(ZX) to an Xreg */ |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 518 | ARM64in_VMov, /* vector reg-reg move, 16, 8 or 4 bytes */ |
| 519 | /* infrastructure */ |
sewardj | 0ad37a9 | 2014-08-29 21:58:03 +0000 | [diff] [blame] | 520 | ARM64in_EvCheck, /* Event check */ |
| 521 | ARM64in_ProfInc /* 64-bit profile counter increment */ |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 522 | } |
| 523 | ARM64InstrTag; |
| 524 | |
| 525 | /* Destinations are on the LEFT (first operand) */ |
| 526 | |
| 527 | typedef |
| 528 | struct { |
| 529 | ARM64InstrTag tag; |
| 530 | union { |
| 531 | /* --- INTEGER INSTRUCTIONS --- */ |
| 532 | /* 64 bit ADD/SUB reg, reg or uimm12<<{0,12} */ |
| 533 | struct { |
| 534 | HReg dst; |
| 535 | HReg argL; |
| 536 | ARM64RIA* argR; |
| 537 | Bool isAdd; |
| 538 | } Arith; |
| 539 | /* 64 or 32 bit CMP reg, reg or aimm (SUB and set flags) */ |
| 540 | struct { |
| 541 | HReg argL; |
| 542 | ARM64RIA* argR; |
| 543 | Bool is64; |
| 544 | } Cmp; |
| 545 | /* 64 bit AND/OR/XOR reg, reg or bitfield-immediate */ |
| 546 | struct { |
| 547 | HReg dst; |
| 548 | HReg argL; |
| 549 | ARM64RIL* argR; |
| 550 | ARM64LogicOp op; |
| 551 | } Logic; |
| 552 | /* 64 bit TST reg, reg or bimm (AND and set flags) */ |
| 553 | struct { |
| 554 | HReg argL; |
| 555 | ARM64RIL* argR; |
| 556 | } Test; |
| 557 | /* 64 bit SHL/SHR/SAR, 2nd arg is reg or imm */ |
| 558 | struct { |
| 559 | HReg dst; |
| 560 | HReg argL; |
| 561 | ARM64RI6* argR; |
| 562 | ARM64ShiftOp op; |
| 563 | } Shift; |
| 564 | /* NOT/NEG/CLZ, 64 bit only */ |
| 565 | struct { |
| 566 | HReg dst; |
| 567 | HReg src; |
| 568 | ARM64UnaryOp op; |
| 569 | } Unary; |
| 570 | /* MOV dst, src -- reg-reg move for integer registers */ |
| 571 | struct { |
| 572 | HReg dst; |
| 573 | HReg src; |
| 574 | } MovI; |
| 575 | /* Pseudo-insn; make a 64-bit immediate */ |
| 576 | struct { |
| 577 | HReg dst; |
| 578 | ULong imm64; |
| 579 | } Imm64; |
| 580 | /* 64-bit load or store */ |
| 581 | struct { |
| 582 | Bool isLoad; |
| 583 | HReg rD; |
| 584 | ARM64AMode* amode; |
| 585 | } LdSt64; |
| 586 | /* zx-32-to-64-bit load, or 32-bit store */ |
| 587 | struct { |
| 588 | Bool isLoad; |
| 589 | HReg rD; |
| 590 | ARM64AMode* amode; |
| 591 | } LdSt32; |
| 592 | /* zx-16-to-64-bit load, or 16-bit store */ |
| 593 | struct { |
| 594 | Bool isLoad; |
| 595 | HReg rD; |
| 596 | ARM64AMode* amode; |
| 597 | } LdSt16; |
| 598 | /* zx-8-to-64-bit load, or 8-bit store */ |
| 599 | struct { |
| 600 | Bool isLoad; |
| 601 | HReg rD; |
| 602 | ARM64AMode* amode; |
| 603 | } LdSt8; |
| 604 | /* Update the guest PC value, then exit requesting to chain |
| 605 | to it. May be conditional. Urr, use of Addr64 implicitly |
| 606 | assumes that wordsize(guest) == wordsize(host). */ |
| 607 | struct { |
| 608 | Addr64 dstGA; /* next guest address */ |
| 609 | ARM64AMode* amPC; /* amode in guest state for PC */ |
| 610 | ARM64CondCode cond; /* can be ARM64cc_AL */ |
| 611 | Bool toFastEP; /* chain to the slow or fast point? */ |
| 612 | } XDirect; |
| 613 | /* Boring transfer to a guest address not known at JIT time. |
| 614 | Not chainable. May be conditional. */ |
| 615 | struct { |
| 616 | HReg dstGA; |
| 617 | ARM64AMode* amPC; |
| 618 | ARM64CondCode cond; /* can be ARM64cc_AL */ |
| 619 | } XIndir; |
| 620 | /* Assisted transfer to a guest address, most general case. |
| 621 | Not chainable. May be conditional. */ |
| 622 | struct { |
| 623 | HReg dstGA; |
| 624 | ARM64AMode* amPC; |
| 625 | ARM64CondCode cond; /* can be ARM64cc_AL */ |
| 626 | IRJumpKind jk; |
| 627 | } XAssisted; |
| 628 | /* CSEL: dst = if cond then argL else argR. cond may be anything. */ |
| 629 | struct { |
| 630 | HReg dst; |
| 631 | HReg argL; |
| 632 | HReg argR; |
| 633 | ARM64CondCode cond; |
| 634 | } CSel; |
| 635 | /* Pseudo-insn. Call target (an absolute address), on given |
| 636 | condition (which could be ARM64cc_AL). */ |
| 637 | struct { |
| 638 | RetLoc rloc; /* where the return value will be */ |
florian | 93a0974 | 2015-01-07 20:14:48 +0000 | [diff] [blame] | 639 | Addr64 target; |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 640 | ARM64CondCode cond; |
| 641 | Int nArgRegs; /* # regs carrying args: 0 .. 8 */ |
| 642 | } Call; |
| 643 | /* move SP by small, signed constant */ |
| 644 | struct { |
| 645 | Int simm; /* needs to be 0 % 16 and in the range -4095 |
| 646 | .. 4095 inclusive */ |
| 647 | } AddToSP; |
| 648 | /* move SP to integer register */ |
| 649 | struct { |
| 650 | HReg dst; |
| 651 | } FromSP; |
| 652 | /* Integer multiply, with 3 variants: |
| 653 | (PLAIN) lo64(64 * 64) |
| 654 | (ZX) hi64(64 *u 64) |
| 655 | (SX) hi64(64 *s 64) |
| 656 | */ |
| 657 | struct { |
| 658 | HReg dst; |
| 659 | HReg argL; |
| 660 | HReg argR; |
| 661 | ARM64MulOp op; |
| 662 | } Mul; |
sewardj | 7d00913 | 2014-02-20 17:43:38 +0000 | [diff] [blame] | 663 | /* LDXR{,H,B} x2, [x4] */ |
| 664 | struct { |
| 665 | Int szB; /* 1, 2, 4 or 8 */ |
| 666 | } LdrEX; |
| 667 | /* STXR{,H,B} w0, x2, [x4] */ |
| 668 | struct { |
| 669 | Int szB; /* 1, 2, 4 or 8 */ |
| 670 | } StrEX; |
| 671 | /* Mem fence. An insn which fences all loads and stores as |
| 672 | much as possible before continuing. On ARM64 we emit the |
| 673 | sequence "dsb sy ; dmb sy ; isb sy", which is probably |
| 674 | total nuclear overkill, but better safe than sorry. */ |
| 675 | struct { |
| 676 | } MFence; |
Elliott Hughes | a0664b9 | 2017-04-18 17:46:52 -0700 | [diff] [blame] | 677 | /* A CLREX instruction. */ |
| 678 | struct { |
| 679 | } ClrEX; |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 680 | /* --- INSTRUCTIONS INVOLVING VECTOR REGISTERS --- */ |
sewardj | 400d6b9 | 2015-03-30 09:01:51 +0000 | [diff] [blame] | 681 | /* ld/st to/from low 16 bits of vec reg, imm offset */ |
| 682 | struct { |
| 683 | Bool isLoad; |
| 684 | HReg hD; |
| 685 | HReg rN; |
| 686 | UInt uimm12; /* 0 .. 8190 inclusive, 0 % 2 */ |
| 687 | } VLdStH; |
| 688 | /* ld/st to/from low 32 bits of vec reg, imm offset */ |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 689 | struct { |
| 690 | Bool isLoad; |
| 691 | HReg sD; |
| 692 | HReg rN; |
| 693 | UInt uimm12; /* 0 .. 16380 inclusive, 0 % 4 */ |
| 694 | } VLdStS; |
sewardj | 400d6b9 | 2015-03-30 09:01:51 +0000 | [diff] [blame] | 695 | /* ld/st to/from low 64 bits of vec reg, imm offset */ |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 696 | struct { |
| 697 | Bool isLoad; |
| 698 | HReg dD; |
| 699 | HReg rN; |
| 700 | UInt uimm12; /* 0 .. 32760 inclusive, 0 % 8 */ |
| 701 | } VLdStD; |
sewardj | 400d6b9 | 2015-03-30 09:01:51 +0000 | [diff] [blame] | 702 | /* ld/st to/from all 128 bits of vec reg, no offset */ |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 703 | struct { |
| 704 | Bool isLoad; |
| 705 | HReg rQ; // data |
| 706 | HReg rN; // address |
| 707 | } VLdStQ; |
| 708 | /* Scalar conversion of int to float. */ |
| 709 | struct { |
| 710 | ARM64CvtOp how; |
| 711 | HReg rD; // dst, a D or S register |
| 712 | HReg rS; // src, a W or X register |
| 713 | } VCvtI2F; |
| 714 | /* Scalar conversion of float to int, w/ specified RM. */ |
| 715 | struct { |
| 716 | ARM64CvtOp how; |
| 717 | HReg rD; // dst, a W or X register |
| 718 | HReg rS; // src, a D or S register |
| 719 | UChar armRM; // ARM encoded RM: |
| 720 | // 00=nearest, 01=+inf, 10=-inf, 11=zero |
| 721 | } VCvtF2I; |
sewardj | 400d6b9 | 2015-03-30 09:01:51 +0000 | [diff] [blame] | 722 | /* Convert between 32-bit and 64-bit FP values (both ways). (FCVT) */ |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 723 | struct { |
| 724 | Bool sToD; /* True: F32->F64. False: F64->F32 */ |
| 725 | HReg dst; |
| 726 | HReg src; |
| 727 | } VCvtSD; |
sewardj | 400d6b9 | 2015-03-30 09:01:51 +0000 | [diff] [blame] | 728 | /* Convert between 16-bit and 32-bit FP values (both ways). (FCVT) */ |
| 729 | struct { |
| 730 | Bool hToS; /* True: F16->F32. False: F32->F16 */ |
| 731 | HReg dst; |
| 732 | HReg src; |
| 733 | } VCvtHS; |
| 734 | /* Convert between 16-bit and 64-bit FP values (both ways). (FCVT) */ |
| 735 | struct { |
| 736 | Bool hToD; /* True: F16->F64. False: F64->F16 */ |
| 737 | HReg dst; |
| 738 | HReg src; |
| 739 | } VCvtHD; |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 740 | /* 64-bit FP unary */ |
| 741 | struct { |
| 742 | ARM64FpUnaryOp op; |
| 743 | HReg dst; |
| 744 | HReg src; |
| 745 | } VUnaryD; |
| 746 | /* 32-bit FP unary */ |
| 747 | struct { |
| 748 | ARM64FpUnaryOp op; |
| 749 | HReg dst; |
| 750 | HReg src; |
| 751 | } VUnaryS; |
| 752 | /* 64-bit FP binary arithmetic */ |
| 753 | struct { |
| 754 | ARM64FpBinOp op; |
| 755 | HReg dst; |
| 756 | HReg argL; |
| 757 | HReg argR; |
| 758 | } VBinD; |
| 759 | /* 32-bit FP binary arithmetic */ |
| 760 | struct { |
| 761 | ARM64FpBinOp op; |
| 762 | HReg dst; |
| 763 | HReg argL; |
| 764 | HReg argR; |
| 765 | } VBinS; |
| 766 | /* 64-bit FP compare */ |
| 767 | struct { |
| 768 | HReg argL; |
| 769 | HReg argR; |
| 770 | } VCmpD; |
| 771 | /* 32-bit FP compare */ |
| 772 | struct { |
| 773 | HReg argL; |
| 774 | HReg argR; |
| 775 | } VCmpS; |
sewardj | e23ec11 | 2014-11-15 16:07:14 +0000 | [diff] [blame] | 776 | /* 32- or 64-bit FP conditional select */ |
| 777 | struct { |
| 778 | HReg dst; |
| 779 | HReg argL; |
| 780 | HReg argR; |
| 781 | ARM64CondCode cond; |
| 782 | Bool isD; |
| 783 | } |
| 784 | VFCSel; |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 785 | /* Move a 32-bit value to/from the FPCR */ |
| 786 | struct { |
| 787 | Bool toFPCR; |
| 788 | HReg iReg; |
| 789 | } FPCR; |
sewardj | 1297218 | 2014-08-04 08:09:47 +0000 | [diff] [blame] | 790 | /* Move a 32-bit value to/from the FPSR */ |
| 791 | struct { |
| 792 | Bool toFPSR; |
| 793 | HReg iReg; |
| 794 | } FPSR; |
sewardj | 606c4ba | 2014-01-26 19:11:14 +0000 | [diff] [blame] | 795 | /* binary vector operation on vector registers */ |
| 796 | struct { |
| 797 | ARM64VecBinOp op; |
| 798 | HReg dst; |
| 799 | HReg argL; |
| 800 | HReg argR; |
| 801 | } VBinV; |
sewardj | f7003bc | 2014-08-18 12:28:02 +0000 | [diff] [blame] | 802 | /* binary vector operation on vector registers. |
| 803 | Dst reg is also a src. */ |
| 804 | struct { |
| 805 | ARM64VecModifyOp op; |
| 806 | HReg mod; |
| 807 | HReg arg; |
| 808 | } VModifyV; |
sewardj | fab0914 | 2014-02-10 10:28:13 +0000 | [diff] [blame] | 809 | /* unary vector operation on vector registers */ |
| 810 | struct { |
| 811 | ARM64VecUnaryOp op; |
| 812 | HReg dst; |
| 813 | HReg arg; |
| 814 | } VUnaryV; |
sewardj | 606c4ba | 2014-01-26 19:11:14 +0000 | [diff] [blame] | 815 | /* vector narrowing, Q -> Q. Result goes in the bottom half |
sewardj | ecedd98 | 2014-08-11 14:02:47 +0000 | [diff] [blame] | 816 | of dst and the top half is zeroed out. Iow one of the |
| 817 | XTN family. */ |
sewardj | 606c4ba | 2014-01-26 19:11:14 +0000 | [diff] [blame] | 818 | struct { |
sewardj | ecedd98 | 2014-08-11 14:02:47 +0000 | [diff] [blame] | 819 | ARM64VecNarrowOp op; |
| 820 | UInt dszBlg2; // 0: 16to8_x8 1: 32to16_x4 2: 64to32_x2 |
| 821 | HReg dst; // Q reg |
| 822 | HReg src; // Q reg |
sewardj | 606c4ba | 2014-01-26 19:11:14 +0000 | [diff] [blame] | 823 | } VNarrowV; |
sewardj | a97dddf | 2014-08-14 22:26:52 +0000 | [diff] [blame] | 824 | /* Vector shift by immediate. For left shifts, |amt| must be |
| 825 | >= 0 and < implied lane size of |op|. For right shifts, |
| 826 | |amt| must be > 0 and <= implied lane size of |op|. Shifts |
| 827 | beyond these ranges are not allowed. */ |
sewardj | e520bb3 | 2014-02-17 11:00:53 +0000 | [diff] [blame] | 828 | struct { |
sewardj | a6b61f0 | 2014-08-17 18:32:14 +0000 | [diff] [blame] | 829 | ARM64VecShiftImmOp op; |
| 830 | HReg dst; |
| 831 | HReg src; |
| 832 | UInt amt; |
sewardj | e520bb3 | 2014-02-17 11:00:53 +0000 | [diff] [blame] | 833 | } VShiftImmV; |
sewardj | ab33a7a | 2014-06-19 22:20:47 +0000 | [diff] [blame] | 834 | struct { |
| 835 | HReg dst; |
| 836 | HReg srcLo; |
| 837 | HReg srcHi; |
| 838 | UInt amtB; |
| 839 | } VExtV; |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 840 | struct { |
| 841 | HReg rQ; |
| 842 | UShort imm; /* Same 1-bit-per-byte encoding as IR */ |
| 843 | } VImmQ; |
| 844 | struct { |
| 845 | HReg rD; |
| 846 | HReg rX; |
| 847 | } VDfromX; |
| 848 | struct { |
| 849 | HReg rQ; |
sewardj | 1297218 | 2014-08-04 08:09:47 +0000 | [diff] [blame] | 850 | HReg rXlo; |
| 851 | } VQfromX; |
| 852 | struct { |
| 853 | HReg rQ; |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 854 | HReg rXhi; |
| 855 | HReg rXlo; |
| 856 | } VQfromXX; |
| 857 | struct { |
| 858 | HReg rX; |
| 859 | HReg rQ; |
| 860 | UInt laneNo; /* either 0 or 1 */ |
| 861 | } VXfromQ; |
sewardj | 85fbb02 | 2014-06-12 13:16:01 +0000 | [diff] [blame] | 862 | struct { |
| 863 | HReg rX; |
| 864 | HReg rDorS; |
| 865 | Bool fromD; |
| 866 | } VXfromDorS; |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 867 | /* MOV dst, src -- reg-reg move for vector registers */ |
| 868 | struct { |
| 869 | UInt szB; // 16=mov qD,qS; 8=mov dD,dS; 4=mov sD,sS |
| 870 | HReg dst; |
| 871 | HReg src; |
| 872 | } VMov; |
| 873 | struct { |
| 874 | ARM64AMode* amCounter; |
| 875 | ARM64AMode* amFailAddr; |
| 876 | } EvCheck; |
sewardj | 0ad37a9 | 2014-08-29 21:58:03 +0000 | [diff] [blame] | 877 | struct { |
| 878 | /* No fields. The address of the counter to inc is |
| 879 | installed later, post-translation, by patching it in, |
| 880 | as it is not known at translation time. */ |
| 881 | } ProfInc; |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 882 | } ARM64in; |
| 883 | } |
| 884 | ARM64Instr; |
| 885 | |
sewardj | 633d9db | 2014-06-25 12:19:02 +0000 | [diff] [blame] | 886 | |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 887 | extern ARM64Instr* ARM64Instr_Arith ( HReg, HReg, ARM64RIA*, Bool isAdd ); |
| 888 | extern ARM64Instr* ARM64Instr_Cmp ( HReg, ARM64RIA*, Bool is64 ); |
| 889 | extern ARM64Instr* ARM64Instr_Logic ( HReg, HReg, ARM64RIL*, ARM64LogicOp ); |
| 890 | extern ARM64Instr* ARM64Instr_Test ( HReg, ARM64RIL* ); |
| 891 | extern ARM64Instr* ARM64Instr_Shift ( HReg, HReg, ARM64RI6*, ARM64ShiftOp ); |
| 892 | extern ARM64Instr* ARM64Instr_Unary ( HReg, HReg, ARM64UnaryOp ); |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 893 | extern ARM64Instr* ARM64Instr_MovI ( HReg, HReg ); |
| 894 | extern ARM64Instr* ARM64Instr_Imm64 ( HReg, ULong ); |
| 895 | extern ARM64Instr* ARM64Instr_LdSt64 ( Bool isLoad, HReg, ARM64AMode* ); |
| 896 | extern ARM64Instr* ARM64Instr_LdSt32 ( Bool isLoad, HReg, ARM64AMode* ); |
| 897 | extern ARM64Instr* ARM64Instr_LdSt16 ( Bool isLoad, HReg, ARM64AMode* ); |
| 898 | extern ARM64Instr* ARM64Instr_LdSt8 ( Bool isLoad, HReg, ARM64AMode* ); |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 899 | extern ARM64Instr* ARM64Instr_XDirect ( Addr64 dstGA, ARM64AMode* amPC, |
| 900 | ARM64CondCode cond, Bool toFastEP ); |
| 901 | extern ARM64Instr* ARM64Instr_XIndir ( HReg dstGA, ARM64AMode* amPC, |
| 902 | ARM64CondCode cond ); |
| 903 | extern ARM64Instr* ARM64Instr_XAssisted ( HReg dstGA, ARM64AMode* amPC, |
| 904 | ARM64CondCode cond, IRJumpKind jk ); |
| 905 | extern ARM64Instr* ARM64Instr_CSel ( HReg dst, HReg argL, HReg argR, |
| 906 | ARM64CondCode cond ); |
florian | 93a0974 | 2015-01-07 20:14:48 +0000 | [diff] [blame] | 907 | extern ARM64Instr* ARM64Instr_Call ( ARM64CondCode, Addr64, Int nArgRegs, |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 908 | RetLoc rloc ); |
| 909 | extern ARM64Instr* ARM64Instr_AddToSP ( Int simm ); |
| 910 | extern ARM64Instr* ARM64Instr_FromSP ( HReg dst ); |
| 911 | extern ARM64Instr* ARM64Instr_Mul ( HReg dst, HReg argL, HReg argR, |
| 912 | ARM64MulOp op ); |
sewardj | 7d00913 | 2014-02-20 17:43:38 +0000 | [diff] [blame] | 913 | extern ARM64Instr* ARM64Instr_LdrEX ( Int szB ); |
| 914 | extern ARM64Instr* ARM64Instr_StrEX ( Int szB ); |
| 915 | extern ARM64Instr* ARM64Instr_MFence ( void ); |
Elliott Hughes | a0664b9 | 2017-04-18 17:46:52 -0700 | [diff] [blame] | 916 | extern ARM64Instr* ARM64Instr_ClrEX ( void ); |
sewardj | 400d6b9 | 2015-03-30 09:01:51 +0000 | [diff] [blame] | 917 | extern ARM64Instr* ARM64Instr_VLdStH ( Bool isLoad, HReg sD, HReg rN, |
| 918 | UInt uimm12 /* 0 .. 8190, 0 % 2 */ ); |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 919 | extern ARM64Instr* ARM64Instr_VLdStS ( Bool isLoad, HReg sD, HReg rN, |
| 920 | UInt uimm12 /* 0 .. 16380, 0 % 4 */ ); |
| 921 | extern ARM64Instr* ARM64Instr_VLdStD ( Bool isLoad, HReg dD, HReg rN, |
| 922 | UInt uimm12 /* 0 .. 32760, 0 % 8 */ ); |
| 923 | extern ARM64Instr* ARM64Instr_VLdStQ ( Bool isLoad, HReg rQ, HReg rN ); |
| 924 | extern ARM64Instr* ARM64Instr_VCvtI2F ( ARM64CvtOp how, HReg rD, HReg rS ); |
| 925 | extern ARM64Instr* ARM64Instr_VCvtF2I ( ARM64CvtOp how, HReg rD, HReg rS, |
| 926 | UChar armRM ); |
| 927 | extern ARM64Instr* ARM64Instr_VCvtSD ( Bool sToD, HReg dst, HReg src ); |
sewardj | 400d6b9 | 2015-03-30 09:01:51 +0000 | [diff] [blame] | 928 | extern ARM64Instr* ARM64Instr_VCvtHS ( Bool hToS, HReg dst, HReg src ); |
| 929 | extern ARM64Instr* ARM64Instr_VCvtHD ( Bool hToD, HReg dst, HReg src ); |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 930 | extern ARM64Instr* ARM64Instr_VUnaryD ( ARM64FpUnaryOp op, HReg dst, HReg src ); |
| 931 | extern ARM64Instr* ARM64Instr_VUnaryS ( ARM64FpUnaryOp op, HReg dst, HReg src ); |
| 932 | extern ARM64Instr* ARM64Instr_VBinD ( ARM64FpBinOp op, HReg, HReg, HReg ); |
| 933 | extern ARM64Instr* ARM64Instr_VBinS ( ARM64FpBinOp op, HReg, HReg, HReg ); |
| 934 | extern ARM64Instr* ARM64Instr_VCmpD ( HReg argL, HReg argR ); |
| 935 | extern ARM64Instr* ARM64Instr_VCmpS ( HReg argL, HReg argR ); |
sewardj | e23ec11 | 2014-11-15 16:07:14 +0000 | [diff] [blame] | 936 | extern ARM64Instr* ARM64Instr_VFCSel ( HReg dst, HReg argL, HReg argR, |
| 937 | ARM64CondCode cond, Bool isD ); |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 938 | extern ARM64Instr* ARM64Instr_FPCR ( Bool toFPCR, HReg iReg ); |
sewardj | 1297218 | 2014-08-04 08:09:47 +0000 | [diff] [blame] | 939 | extern ARM64Instr* ARM64Instr_FPSR ( Bool toFPSR, HReg iReg ); |
sewardj | 606c4ba | 2014-01-26 19:11:14 +0000 | [diff] [blame] | 940 | extern ARM64Instr* ARM64Instr_VBinV ( ARM64VecBinOp op, HReg, HReg, HReg ); |
sewardj | f7003bc | 2014-08-18 12:28:02 +0000 | [diff] [blame] | 941 | extern ARM64Instr* ARM64Instr_VModifyV ( ARM64VecModifyOp, HReg, HReg ); |
sewardj | fab0914 | 2014-02-10 10:28:13 +0000 | [diff] [blame] | 942 | extern ARM64Instr* ARM64Instr_VUnaryV ( ARM64VecUnaryOp op, HReg, HReg ); |
sewardj | ecedd98 | 2014-08-11 14:02:47 +0000 | [diff] [blame] | 943 | extern ARM64Instr* ARM64Instr_VNarrowV ( ARM64VecNarrowOp op, UInt dszBlg2, |
| 944 | HReg dst, HReg src ); |
sewardj | a6b61f0 | 2014-08-17 18:32:14 +0000 | [diff] [blame] | 945 | extern ARM64Instr* ARM64Instr_VShiftImmV ( ARM64VecShiftImmOp op, |
sewardj | e520bb3 | 2014-02-17 11:00:53 +0000 | [diff] [blame] | 946 | HReg dst, HReg src, UInt amt ); |
sewardj | ab33a7a | 2014-06-19 22:20:47 +0000 | [diff] [blame] | 947 | extern ARM64Instr* ARM64Instr_VExtV ( HReg dst, |
| 948 | HReg srcLo, HReg srcHi, UInt amtB ); |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 949 | extern ARM64Instr* ARM64Instr_VImmQ ( HReg, UShort ); |
| 950 | extern ARM64Instr* ARM64Instr_VDfromX ( HReg rD, HReg rX ); |
sewardj | 1297218 | 2014-08-04 08:09:47 +0000 | [diff] [blame] | 951 | extern ARM64Instr* ARM64Instr_VQfromX ( HReg rQ, HReg rXlo ); |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 952 | extern ARM64Instr* ARM64Instr_VQfromXX( HReg rQ, HReg rXhi, HReg rXlo ); |
| 953 | extern ARM64Instr* ARM64Instr_VXfromQ ( HReg rX, HReg rQ, UInt laneNo ); |
sewardj | 85fbb02 | 2014-06-12 13:16:01 +0000 | [diff] [blame] | 954 | extern ARM64Instr* ARM64Instr_VXfromDorS ( HReg rX, HReg rDorS, Bool fromD ); |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 955 | extern ARM64Instr* ARM64Instr_VMov ( UInt szB, HReg dst, HReg src ); |
| 956 | |
| 957 | extern ARM64Instr* ARM64Instr_EvCheck ( ARM64AMode* amCounter, |
| 958 | ARM64AMode* amFailAddr ); |
sewardj | 0ad37a9 | 2014-08-29 21:58:03 +0000 | [diff] [blame] | 959 | extern ARM64Instr* ARM64Instr_ProfInc ( void ); |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 960 | |
florian | d8c64e0 | 2014-10-08 08:54:44 +0000 | [diff] [blame] | 961 | extern void ppARM64Instr ( const ARM64Instr* ); |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 962 | |
| 963 | |
| 964 | /* Some functions that insulate the register allocator from details |
| 965 | of the underlying instruction set. */ |
florian | d8c64e0 | 2014-10-08 08:54:44 +0000 | [diff] [blame] | 966 | extern void getRegUsage_ARM64Instr ( HRegUsage*, const ARM64Instr*, Bool ); |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 967 | extern void mapRegs_ARM64Instr ( HRegRemap*, ARM64Instr*, Bool ); |
florian | d8c64e0 | 2014-10-08 08:54:44 +0000 | [diff] [blame] | 968 | extern Bool isMove_ARM64Instr ( const ARM64Instr*, HReg*, HReg* ); |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 969 | extern Int emit_ARM64Instr ( /*MB_MOD*/Bool* is_profInc, |
florian | d8c64e0 | 2014-10-08 08:54:44 +0000 | [diff] [blame] | 970 | UChar* buf, Int nbuf, const ARM64Instr* i, |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 971 | Bool mode64, |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 972 | VexEndness endness_host, |
florian | 8462d11 | 2014-09-24 15:18:09 +0000 | [diff] [blame] | 973 | const void* disp_cp_chain_me_to_slowEP, |
| 974 | const void* disp_cp_chain_me_to_fastEP, |
| 975 | const void* disp_cp_xindir, |
| 976 | const void* disp_cp_xassisted ); |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 977 | |
| 978 | extern void genSpill_ARM64 ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2, |
| 979 | HReg rreg, Int offset, Bool ); |
| 980 | extern void genReload_ARM64 ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2, |
| 981 | HReg rreg, Int offset, Bool ); |
| 982 | |
sewardj | a5b5022 | 2015-03-26 07:18:32 +0000 | [diff] [blame] | 983 | extern const RRegUniverse* getRRegUniverse_ARM64 ( void ); |
| 984 | |
florian | cacba8e | 2014-12-15 18:58:07 +0000 | [diff] [blame] | 985 | extern HInstrArray* iselSB_ARM64 ( const IRSB*, |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 986 | VexArch, |
florian | d8c64e0 | 2014-10-08 08:54:44 +0000 | [diff] [blame] | 987 | const VexArchInfo*, |
| 988 | const VexAbiInfo*, |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 989 | Int offs_Host_EvC_Counter, |
| 990 | Int offs_Host_EvC_FailAddr, |
| 991 | Bool chainingAllowed, |
| 992 | Bool addProfInc, |
florian | dcd6d23 | 2015-01-02 17:32:21 +0000 | [diff] [blame] | 993 | Addr max_ga ); |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 994 | |
| 995 | /* How big is an event check? This is kind of a kludge because it |
| 996 | depends on the offsets of host_EvC_FAILADDR and |
| 997 | host_EvC_COUNTER. */ |
florian | 7ce2cc8 | 2015-01-10 16:10:58 +0000 | [diff] [blame] | 998 | extern Int evCheckSzB_ARM64 (void); |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 999 | |
| 1000 | /* Perform a chaining and unchaining of an XDirect jump. */ |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 1001 | extern VexInvalRange chainXDirect_ARM64 ( VexEndness endness_host, |
| 1002 | void* place_to_chain, |
florian | 7d6f81d | 2014-09-22 21:43:37 +0000 | [diff] [blame] | 1003 | const void* disp_cp_chain_me_EXPECTED, |
| 1004 | const void* place_to_jump_to ); |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 1005 | |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 1006 | extern VexInvalRange unchainXDirect_ARM64 ( VexEndness endness_host, |
| 1007 | void* place_to_unchain, |
florian | 7d6f81d | 2014-09-22 21:43:37 +0000 | [diff] [blame] | 1008 | const void* place_to_jump_to_EXPECTED, |
| 1009 | const void* disp_cp_chain_me ); |
sewardj | c6acaa4 | 2014-02-19 17:42:59 +0000 | [diff] [blame] | 1010 | |
sewardj | 0ad37a9 | 2014-08-29 21:58:03 +0000 | [diff] [blame] | 1011 | /* Patch the counter location into an existing ProfInc point. */ |
| 1012 | extern VexInvalRange patchProfInc_ARM64 ( VexEndness endness_host, |
| 1013 | void* place_to_patch, |
florian | 7d6f81d | 2014-09-22 21:43:37 +0000 | [diff] [blame] | 1014 | const ULong* location_of_counter ); |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 1015 | |
| 1016 | |
| 1017 | #endif /* ndef __VEX_HOST_ARM64_DEFS_H */ |
| 1018 | |
| 1019 | /*---------------------------------------------------------------*/ |
| 1020 | /*--- end host_arm64_defs.h ---*/ |
| 1021 | /*---------------------------------------------------------------*/ |