- 07a54cc Allow easy switching of guest-host arch pairs using ifdefs. by sewardj · 20 years ago
- e908c42 A couple of debugging hacks to allow work to proceed on a front end by sewardj · 20 years ago
- 813ce9e Make a start on the amd64 assembler. Bleh. by sewardj · 20 years ago
- 53df061 'movabsq' instruction definitions. by sewardj · 20 years ago
- f73b94a Fix bogus assertion. (How long has that been there?) by sewardj · 20 years ago
- 7f039c4 A few more amd64 isel cases. by sewardj · 20 years ago
- e1d857b Yay! return.orig gets totally chomped! by cerion · 20 years ago
- 487e4c9 Support host-ppc32... by cerion · 20 years ago
- bcf8c3e Get the PPC32 back-end show on the road. by cerion · 20 years ago
- 98d105a Represent floats in guest_ppc32 by cerion · 20 years ago
- 78f714b Fixed 'branch op to read pc', plus cleaned up a little by cerion · 20 years ago
- df772dc A simpler .orig file, which (1) has no Altivec insns, and (2) is by sewardj · 20 years ago
- 05b3b6a Fix many instruction selection cases, including function calls. by sewardj · 20 years ago
- 7883018 Record some shortcomings (comment-only change). by sewardj · 20 years ago
- cdcf00b Fix wrong comment. by sewardj · 20 years ago
- 45552a9 Reworked dis_branch to be somewhat simpler (optimiser can now simplify the IR well). by cerion · 20 years ago
- ab054e3 Using new IR div ops by cerion · 20 years ago
- 5c8a0cb Added new ir ops Iop_DivU32, Iop_DivS32 by cerion · 20 years ago
- ec842a9 tiny correction to guest-arm branch op by cerion · 20 years ago
- 5456081 Undoing mistaken commit of r825. by cerion · 20 years ago
- c194477 tiny correction to guest-arm branch by cerion · 20 years ago
- b0004f7 Fixed nand, and added pass-through for a couple of rather strange instructions... by cerion · 20 years ago
- 995bc36 - Added lots of printfs on decode failures. by cerion · 20 years ago
- f67eadf Fix enough stuff so that the first bb goes through, up to and by sewardj · 20 years ago
- 3a5cf13 Make the guest-state-size 64-bit aligned, else some assertion or other by sewardj · 20 years ago
- f01659e Fix out-of-date comment. by sewardj · 20 years ago
- 9db81c0 Make the x86 back end happy to chew through IR from the ppc32 front by sewardj · 20 years ago
- 26d07b2 Lots of cleanup Couple of new ops - lswx, memsync stuff by cerion · 20 years ago
- 8258a8c Do a bunch more basic integer instruction selection cases. by sewardj · 20 years ago
- df53045 It seems we never generate x86 rotate insns, so get rid of these. by sewardj · 20 years ago
- 614b3fb My first AMD64 instruction. Ga. Goo. (etc) by sewardj · 20 years ago
- c77afb1 Remove trivial CSE. by sewardj · 20 years ago
- 0949836 a lonely eqv op... by cerion · 20 years ago
- 62bec57 Cleaned up clean-helper functions Added various vasserts around the place. by cerion · 20 years ago
- 01a9e80 Deal with undecodable instructions by generating code to yield with by sewardj · 20 years ago
- c33671d Get the AMD64 back-end show on the road. by sewardj · 20 years ago
- c0250e4 Fix comment error. by sewardj · 20 years ago
- c342f4a Still more ops... stores/loads, moves to/from spr's by cerion · 20 years ago
- 9ee4f7d Get rid of debug printing. by sewardj · 20 years ago
- 5dd5eb9 Fix misc naming things (unimportant) by sewardj · 20 years ago
- b7a0a11 Add files in priv/host-amd64 to build system by sewardj · 20 years ago
- c19d5e1 More ops.... arith, loads, stores, branch, shifts, move from/to spr by cerion · 20 years ago
- a3e9830 Files for amd64 back end. by sewardj · 20 years ago
- ff52a7e New directory. by sewardj · 20 years ago
- 0ec57c5 PowerPC-32 has at at least two variant (with and without Altivec). by sewardj · 20 years ago
- 2d49b43 Typechecker (icc) police. by sewardj · 20 years ago
- 227458e Flee from relentless persecution by icc's typechecker :-) by sewardj · 20 years ago
- 7eaa7cf Fix various minor things found by auto-test by sewardj · 20 years ago
- 807598d Autotest dregs by sewardj · 20 years ago
- 1f2adef Wibble by sewardj · 20 years ago
- 44997f2 some stores and loads by cerion · 20 years ago
- 95cbcc1 Sync with test2.orig by sewardj · 20 years ago
- 03b07cc Add enough cases to handle all of orig_amd64/test2.orig. by sewardj · 20 years ago
- 343b9d0 Add two new primops needed by the amd64 front end. by sewardj · 20 years ago
- d78e3f4 Make parseable by test_main by sewardj · 20 years ago
- 45b70ff done int rotates by cerion · 20 years ago
- cf00446 filled out more ops (mostly arith + logic), plus cleaned up a little by cerion · 20 years ago
- 8c3adda Added framework for mem sync, processor control, and cache management instructions by cerion · 20 years ago
- 826fdf7 set client-request magic sequence in toIR.c by cerion · 20 years ago
- 645c930 Added framework for rotates, shifts, loads, stores (plus DIPs all round) by cerion · 20 years ago
- 0ce3d95 Set comments and naming convention of bitfields back to _normality_, i.e. bit 0 = lsb (*0%£@% ibm docs...) by cerion · 20 years ago
- d23be4e Added store instr groundwork by cerion · 20 years ago
- 04bda6d More stuff for automated testing of the fledgling amd64 front end. by sewardj · 20 years ago
- 82cb881 Add usage instructions by sewardj · 20 years ago
- 4b03f61 Program to assist in automated verification of the amd64 front end. by sewardj · 20 years ago
- a299b3d Sync with test1.orig by sewardj · 20 years ago
- e941eea Half-hearted attempt to make instruction disassembly print more by sewardj · 20 years ago
- ebf362a Fix somewhat dubious-look parentheses (I'm sure it was OK, but still ...) by sewardj · 20 years ago
- 73947ef Remove endian-hack (proper solution by j, rev776) by cerion · 20 years ago
- 684aa95 Fish ppc32 instruction words out of memory bigendianly regardless of by sewardj · 20 years ago
- 932ad94 Okayyyyy, I'm a twit. by cerion · 20 years ago
- aabdfbf - Set up proper support for PPC32 archictecture - Wrote the OR ops by cerion · 20 years ago
- 163cd16 Baseline inputs for test1.orig. by sewardj · 20 years ago
- 0faa4e2 Give it a sensible name. by sewardj · 20 years ago
- 7aa4bbc Added dis_int_cmp, dis_int_logic functions by cerion · 20 years ago
- 118b23e more insns: rotates, shifts, setcc, sub, xor, nop by sewardj · 20 years ago
- 364506c wibble by sewardj · 20 years ago
- 3fc67f2 More fiddling with flags. by sewardj · 20 years ago
- 7a24055 Build fixes for icc in ultra-paranoid mode. This may not in the end by sewardj · 20 years ago
- c68d460 Ahem: PPC_FLAGS -> PPC32G_FLAGS by cerion · 20 years ago
- ae69462 - Added ops enum for xer ov,ca flag calculation by cerion · 20 years ago
- 55dbb26 more insns: push, pop, not, neg. by sewardj · 20 years ago
- ba681be More fixes. by sewardj · 20 years ago
- 5e52529 more insns: unsigned widening moves (MOVZ..) by sewardj · 20 years ago
- aa15f31 Fix various "bugs" in this input. by sewardj · 20 years ago
- 1389d4d More instructions: moves, and conditional jumps. by sewardj · 20 years ago
- e9460bd Change a couple of panics into decode failures, which is what they should be. by sewardj · 20 years ago
- 43e336c Mess around a bit with icc's (jolly useful) collection of ultra-paranoid flags. by sewardj · 20 years ago
- 8c332e2 Fix various type inconsistencies picked up by icc running in by sewardj · 20 years ago
- 32b2bbe Do more insns: inc idiv imul by sewardj · 20 years ago
- 91ad536 Cleaned up and filled out: by cerion · 20 years ago
- 354e5c6 amd64 front end marches ever onwards. by sewardj · 20 years ago
- 3ca55a1 Hack on through the undergrowth. Still a long way from anything working. by sewardj · 20 years ago
- b5710b8 Add a folding rule for a very common idiom of the amd64 front end. by sewardj · 20 years ago
- 4206584 Sync with ./Makefile changes by sewardj · 20 years ago
- a340ee8 Fix spelling error in error msg. Duh. by sewardj · 20 years ago
- 2f959cc Try and get the amd64 address mode mess sorted out a bit. by sewardj · 20 years ago
- be6a8a1 Verify that the x86 address mode decoder is really right, and reword a by sewardj · 20 years ago
- 1515db9 changed all occurences of ppc to ppc32 (filenames and text) by cerion · 20 years ago
- db1941a oops, more cpustate stuff by cerion · 20 years ago