Gitiles
Code Review Sign In
gerrit-public.fairphone.software / platform / external / valgrind / 15064763ec2772d517dae47fd52202eda037bc2e
  1. 1506476 Fix, Add support for the Power PC Program Priority Register by carll · 9 years ago
  2. ae34a19 by carll · 9 years ago
  3. ed013fe Add support for the Power PC Program Priority Register by carll · 9 years ago
  4. c7910f4 ppc: The functions dis_dfp_fmt_conv and dis_dfp_exponent_test by florian · 9 years ago
  5. 9ec12ea Improve the spechelper for S390_CC_OP_TEST_UNDER_MASK_16. Fixes BZ #352284. by florian · 9 years ago
  6. ea602a7 iselStmt, case Ist_Exit: handle the same assisted transfer cases that by sewardj · 9 years ago
  7. 278c3fa Further kludge stack alignment issues in x86g_dirtyhelper_FXRSTOR. by sewardj · 9 years ago
  8. b53f948 s390: Add support for fixbr(a) instructions. by florian · 9 years ago
  9. 59d2075 Fix undefined behaviours (left shifting a negative value) by florian · 9 years ago
  10. 785952d Update copyright dates, to include 2015. No functional change. by sewardj · 9 years ago
  11. 543ad88 Reading from TPIDRURO_EL0 and PMUSERENR_EL0: make these properly by sewardj · 9 years ago
  12. 61d7d98 Implement reading from PMUSERENR_EL0, making it return zero. by sewardj · 9 years ago
  13. e3115c1 Implement YIELD. Followup to #348377. by sewardj · 9 years ago
  14. 5e65812 Implement YIELD (encodings T1 and A1). Fixes #348377. by sewardj · 9 years ago
  15. f3ae738 Implement VCVT.{S,U}32.F32, S[n], S[n], #imm. Fixes 342783. by sewardj · 9 years ago
  16. f88e39d Loosen guarding conditions on "mov.w Reg, Reg" so as to allow by sewardj · 9 years ago
  17. 48453e3 Implement PRFM (register). Fixes #345177. by sewardj · 9 years ago
  18. e66a247 vex x86->IR: unhandled instruction bytes: 0x66 0xF 0x3A 0xB (ROUNDSD) on OS X by rhyskidd · 9 years ago
  19. 9497f04 Handle PCMPxSTRx case 0x18. Fixes #348574. by sewardj · 9 years ago
  20. 2e3b5b0 Handle PCMPxSTRx case 0x42. Fixes #339820. by sewardj · 9 years ago
  21. 245855c Fix a bunch of missing AVX VCMPPD/VCMPPS cases. by sewardj · 9 years ago
  22. 70dbeb0 Implement XSAVE/XRSTOR for AVX (state components 0, 1 and 2) by sewardj · 9 years ago
  23. d70215f Removed unused code that has been lying around since the major refactoring by sewardj · 9 years ago
  24. b173774 Fix printf format inconsistencies as pointed out by GCC's -Wformat-signedness. by florian · 9 years ago
  25. 1f47ae2 mips64: make cavium CvmCount register accessible via rdhwr by petarj · 9 years ago
  26. 3e5d82d Bug 345248 - add support for Solaris OS in valgrind by sewardj · 9 years ago
  27. de8674f Fix an obvious typo as reported by dcb314@hotmail.com in BZ #350251. by florian · 9 years ago
  28. b181f37 mips: emit addiu instead of addi by petarj · 9 years ago
  29. 6d0b015 s390: Add support for FIEBR(A) and FIDBR(A). by florian · 9 years ago
  30. 32de776 Fix a bug for TileGX platform found by instruction tests. by zliu · 9 years ago
  31. 4872906 Add some functions for misaligned load/store support, and use them by sewardj · 9 years ago
  32. d4ebe7c Fix condition to avoid that decode[] is indexed out-of-bounds. by florian · 9 years ago
  33. 06c2573 Remove unused computations. Spotted by Coverity. by florian · 9 years ago
  34. 095b4cb * Fix ubsan failures in mullS64 due to signed integer overflow. by sewardj · 9 years ago
  35. a52a638 mips64: do not use 64-bit loads for lwl/lwr instructions by petarj · 9 years ago
  36. 36f940a Fix a few undefined shift operations as spotted by ubsan. by florian · 9 years ago
  37. 7ffce01 * x86: on an SSE2 only host, Valgrind in 32 bits now claims to be a Pentium 4. by philippe · 9 years ago
  38. 6d7c8e4 A SSE2 only CPU was reported to the guest as a SSE3 CPU. by philippe · 9 years ago
  39. 94318d0 mips64: add support for Cavium LHX by petarj · 9 years ago
  40. 24e0c13 Just a dummy white space change to record the fact that in by florian · 9 years ago
  41. bc2c60d Fix a condition that was always true. Found by cppcheck. See BZ #348565. by florian · 9 years ago
  42. b6bea7d Opps, missed a change in the previous patch. Forgot to remove the format by carll · 9 years ago
  43. 646a4fa The dcbt and dcbtst instructions provide a non-zero hint that describes by carll · 9 years ago
  44. d937beb Bug #348247. Fix SUBQ 0, long long sub/cmp, then O (overflow) case. by mjw · 9 years ago
  45. 5434227 Cleanups to allow compilation with -Wold-style-declaration. by florian · 9 years ago
  46. 0c4e9e8 Improve the error messages for the PPC platform to be more clear when Valgrind detects that by carll · 9 years ago
  47. 80d145c Remove VexGuestTILEGXStateAlignment as the guest state size of any architecture by florian · 9 years ago
  48. 486db12 Add support for the TEXASRU register. This register contains information on by carll · 9 years ago
  49. e054218 Add spec rules for EQ, MI, PL, GT and LE after COPY. These result by sewardj · 9 years ago
  50. 999ef56 Fix for an error in the stq, stqcx, lqarx and lq instructions with LE. by carll · 9 years ago
  51. d826889 Add support for the lbarx, lharx, stbcx and sthcs instructions. by carll · 9 years ago
  52. bc6db6e The vbpermq for Powerpc64 big endian has the same issue as the little by carll · 9 years ago
  53. 256df59 The following regression tests failures occur on PPC64 little endian only. by carll · 9 years ago
  54. 009b5fc Add Iop_Add8, Iop_Add16 and other 8 or 16 bit ALU Iop in the host_tilegx_isel.c by zliu · 9 years ago
  55. f2349b7 Removed "extern" by zliu · 9 years ago
  56. 32bf413 Removed #if __tilegx__ ... #endif in guest_tilegx_toIR.c by zliu · 9 years ago
  57. b597f20 Fix the evCheck assertion for TileGX by zliu · 9 years ago
  58. 6faff00 Remove unused function "lshift". by sewardj · 9 years ago
  59. 7e5aa0d VEX side for revision 15084 (multi arch testing) by philippe · 9 years ago
  60. 0de8019 Add a port to Linux/TileGx. Zhi-Gang Liu (zliu@tilera.com) VEX aspects. by sewardj · 9 years ago
  61. 012d5f5 Fix a typo in the example given in the comment by philippe · 9 years ago
  62. 8bb1c9e x86 front and back ends: track vex r3120, which changed the type of by sewardj · 9 years ago
  63. cd4637e amd64 front and back ends: track the change of type of Iop_Sqrt32Fx4 by sewardj · 9 years ago
  64. 4b21c3d arm64: implement FSQRT 2d_2d, 4s_4s, 2s_2s by sewardj · 9 years ago
  65. 2130b34 arm64: add support for the following insns. This completes support by sewardj · 9 years ago
  66. a2cdc9f Tweak STATIC_ASSERT such that there is no warning about an unused by florian · 9 years ago
  67. f886165 Add the standard end of the file marker used elsewhere by philippe · 9 years ago
  68. 6941bc8 Improve comments, add the copyright notice by philippe · 9 years ago
  69. 12b2b5b This patch reduces the size of all tools by about 2MB of text by philippe · 9 years ago
  70. bc0b722 arm64: add support for FCVT{N,M,A,P,Z}{S,U} 2d_2d, 4s_4s, 2s_2s by sewardj · 9 years ago
  71. 400d6b9 arm64: add support for by sewardj · 9 years ago
  72. 3738bfc Add IR level support for 16 bit floating point types (Ity_F16) and add by sewardj · 9 years ago
  73. 1996df0 Add STATIC_ASSERT. Remove VG__STRING. by florian · 9 years ago
  74. a2f370a mips64: extract correct immediate value for Cavium SEQI and SNEI by petarj · 9 years ago
  75. a5b5022 Bug 345215 - Performance improvements for the register allocator by sewardj · 9 years ago
  76. 5775c3c Minor updates to deal with mips32 and mips64. by sewardj · 9 years ago
  77. 514a3b9 Add source dependencies, and improve the 'clean' target. by sewardj · 9 years ago
  78. dee60ed Add z13 (s390). by florian · 9 years ago
  79. d8e3eca r2974 moved the inline definition of LibVEX_Alloc from libvex.h by florian · 9 years ago
  80. 65eec5e Fix build problems. The code has been bitrotting for some time. by florian · 9 years ago
  81. 45f8de6 Fix two undefined behaviours found by ubsan. by florian · 9 years ago
  82. 2f93145 Fix for bugzilla 343597 - ppc64le: incorrect use of offseof macro by carll · 9 years ago
  83. 108e03f Fix a few undefined behaviours that were found by compiling valgrind by florian · 9 years ago
  84. 9edbbd9 Fix problems due to generating Neon instructions on non-Neon capable hosts: by sewardj · 9 years ago
  85. 16caded Add machinery to try and transform A ^ ((A ^ B) & M) into (A ^ ~M) | (B & M). by sewardj · 9 years ago
  86. 2608c69 Enhance the CSE pass so it can common up loads from memory. Disabled by sewardj · 9 years ago
  87. 581cf07 Tidy up of CSE. Create functions irExpr_to_TmpOrConst, by sewardj · 9 years ago
  88. 9e2a008 fold_Expr: add rules Xor8/16/32/64(0,t) ==> t Xor8/16/32/64(t,0) ==> t by sewardj · 9 years ago
  89. f4edb1d arm64: enable all remaining cases in the by sewardj · 9 years ago
  90. 89cefe4 arm64: implement: by sewardj · 9 years ago
  91. 5074b49 Add symbolic constant LibVEX_GUEST_STATE_ALIGN. Use it. by florian · 9 years ago
  92. 8cf6637 Remove an unused macro (which also had undefined behaviours). by florian · 9 years ago
  93. 6a785df Implement FP instructions: by sewardj · 9 years ago
  94. ee3db33 Implement all remaining FP multiple style instructions: by sewardj · 9 years ago
  95. 5cb53e7 Implement all remaining FP min/max style instructions: by sewardj · 9 years ago
  96. 13830dc Implement all remaining FP compare instructions: by sewardj · 9 years ago
  97. 6d5985e Enable FCVTMU Xd,Sn. Fixes #343332. by sewardj · 9 years ago
  98. ca2c3c7 Make a very minor change to the LibVEX_Translate interface (sub-arg of by sewardj · 9 years ago
  99. 18bf154 Fix bug 343802. We need to handle one more special case in the spechelper by cborntra · 9 years ago
  100. 66a5e81 guest_amd64_spechelper: by sewardj · 9 years ago