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gerrit-public.fairphone.software / platform / external / valgrind / 1bdaac5b4b1a10477f8a2f5d6be0fc498b310496 / priv / main_main.c
  1. c3fee0d mips32: Add support for mips32 DSP instruction set. by dejanj · 11 years ago
  2. 78d5ef7 s390: First round of changes to support the PFPO insn. by florian · 11 years ago
  3. 8bde7f1 Implement ARM SDIV and UDIV instructions. Fixes #314178. Partially by sewardj · 12 years ago
  4. cc3d219 AMD64: Add support for AVX2, BMI1, BMI2 and FMA instructions (VEX side). by sewardj · 12 years ago
  5. 818c730 Implement RDTSCP on amd64, finally. This fixes #251569 and dups by sewardj · 12 years ago
  6. b92a954 mips: adding MIPS64LE support to VEX by petarj · 12 years ago
  7. 62140c1 Improve the tree builder in IR optimisation. Allow load expressions to be by florian · 12 years ago
  8. 65ea17e Show the guest->host code expansion ratio when debug-printing translations. by sewardj · 12 years ago
  9. 9061eb3 Eliminate some lameness when writing out hwcaps. by florian · 12 years ago
  10. aec8e05 Move definition of facility bits to libvex_s390x_common.h so we by florian · 12 years ago
  11. 442e51a Make diagnostics for SIGILL more controllable (VEX part). by sewardj · 12 years ago
  12. 3a3d7f1 Use "load on condition" insns, if availably, to implement S390_INSN_COND_MOVE. by florian · 12 years ago
  13. 55085f8 Changes for -Wwrite-strings by florian · 12 years ago
  14. 1ff4756 Constify VEX's external interface. by florian · 12 years ago
  15. 5048192 Pass VexArchInfo to the instrumentation functions. by florian · 12 years ago
  16. f192a39 Add data structures for cache representation to libvex.h: by florian · 12 years ago
  17. f0fa1be s390: Update IR generation for the SRNM insn. by florian · 12 years ago
  18. 4b8efad Support the variety of "convert to/from fixed" and "load rounded" opcodes by florian · 12 years ago
  19. e75dafa s390: Generate an emulation failure if an insn is encountered that by florian · 12 years ago
  20. 60b665b s390: Add floating point extension facility to hwcaps. by florian · 12 years ago
  21. 8c88cb6 s390: Add support for the ecag insn. Patch from Divya Vyas by florian · 12 years ago
  22. c5c669b On s390: Terminate the superblock with Ijk_EmFail if an stckf insn by florian · 12 years ago
  23. a4c3669 s390: Add STCKF hardware facility to hwcaps. by florian · 12 years ago
  24. 4e0083e On s390: Terminate the superblock with Ijk_EmFail if an stfle insn by florian · 12 years ago
  25. 6ef84be Followup to r2483, purely mechanical. Rename: by florian · 12 years ago
  26. 33b0243 Rename libvex_emwarn.h to libvex_emnote.h and fix all by florian · 12 years ago
  27. 25e5473 Update copyright dates to include 2012. by sewardj · 12 years ago
  28. c8e2f98 VEX part (remove --vex-iropt-precise-memory-exns, add --vex-iropt-register-updates) by philippe · 12 years ago
  29. d0e5fe7 Merge in a port for mips32-linux, by Petar Jovanovic and Dejan Jevtic, by sewardj · 12 years ago
  30. 420bfa9 Put the Triop member into a separate struct (IRTriop) and link to that by florian · 12 years ago
  31. 96d7cc3 Put the Qop member into a separate struct (IRQop) and link to that by florian · 12 years ago
  32. c9069f2 Enhance the guest state effects notation on IRDirty calls, so as to be by sewardj · 12 years ago
  33. d6f38b3 Reduce size of an IRStmt from 40 bytes to 32 bytes on LP64 by florian · 12 years ago
  34. b5e17b9 Fix feature recognition on AMD Bulldozer following the recent AVX by sewardj · 12 years ago
  35. c4530ae Add initial support for Intel AVX instructions (VEX side). by sewardj · 12 years ago
  36. 79bee4b Add ETF3 facility (VEX bits). Part of fixing Bugzilla #289839. by florian · 13 years ago
  37. f350a42 Add a feature check flag for AVX. by sewardj · 13 years ago
  38. fadbbe2 (stats only) Let the callers of LibVEX_Translate know how many guest by sewardj · 13 years ago
  39. 90ece04 Fix debug print for hwcaps adding stfle ad etf2. by florian · 13 years ago
  40. db01409 Merge branches/TCHAIN from r2271 (its creation point) into trunk. by sewardj · 13 years ago
  41. f252de5 Changes to make t-chaining work on ppc64-linux. More fun than a by sewardj · 13 years ago
  42. 9e1cf15 Fill in some more bits to do with t-chaining for ppc64 by sewardj · 13 years ago
  43. 3dee849 Add translation chaining support for ppc32 (tested) and to by sewardj · 13 years ago
  44. 8844a63 Translation chaining for s390. To be debugged. by florian · 13 years ago
  45. c6f970f Add translation chaining support for amd64, x86 and ARM (VEX side). See #296422. by sewardj · 13 years ago
  46. c66d6fa Fixes for capabilities checking w.r.t. Power DFP instructions (VEX by sewardj · 13 years ago
  47. e6c53e0 Update all copyright dates, from 20xy-2010 to 20xy-2011. by sewardj · 13 years ago
  48. 2eeeb9b Document and assert that needs_self_check of VexTranslateArgs must not be NULL. by florian · 13 years ago
  49. bc161a4 Change the interface to LibVEX_Translate slightly, so as to make the by sewardj · 13 years ago
  50. 010ac54 x86 and amd64 back ends: when generating transfers back to the by sewardj · 13 years ago
  51. d07b856 s390x: fpr - gpr transfer facility by sewardj · 14 years ago
  52. 66d5ef2 Add support for IBM Power ISA 2.06 -- stage 1. Bug #267630 and by sewardj · 14 years ago
  53. 652b56a s390x: reconsider "long displacement" requirement. We currently by sewardj · 14 years ago
  54. 2019a97 Add a port to IBM z/Architecture (s390x) running Linux -- VEX by sewardj · 14 years ago
  55. e971c6a Support the DCBZL instruction. Also, query the host CPU at startup by sewardj · 14 years ago
  56. ec0d9a0 Merge from branches/THUMB: hwcaps for ARM. May get simplified since by sewardj · 14 years ago
  57. 536fbab Only decode LZCNT if the host supports it, since otherwise we risk by sewardj · 14 years ago
  58. 69d98e3 Implement SSE4 instructions: PCMPGTQ PMAXUD PMINUD PMAXSB PMINSB PMULLD by sewardj · 14 years ago
  59. 752f906 Update copyright dates to 2010 and change license to standard GPL2+. by sewardj · 15 years ago
  60. 984d9b1 by sewardj · 15 years ago
  61. 2a1ed8e Make the x86 and amd64 back ends use the revised prototypes for by sewardj · 15 years ago
  62. 6c299f3 Merge r1925:1948 from branches/ARM. This temporarily breaks all other by sewardj · 15 years ago
  63. 01f8cce Print raw machine code in an easier-to-parse way. by sewardj · 15 years ago
  64. 3187dc7 Get rid of LibVEX_Version(). by sewardj · 15 years ago
  65. ff99b07 Unbreak the svn-version thing following r1904. by sewardj · 15 years ago
  66. cef7d3e by sewardj · 15 years ago[Renamed (97%) from priv/main/vex_main.c]
  67. e9d8a26 Merge in branches/DCAS: by sewardj · 15 years ago
  68. 2e28ac4 by sewardj · 16 years ago
  69. a26d820 Update copyright dates ("200X-2007" --> "200X-2008"). by sewardj · 17 years ago
  70. be1b6ff by sewardj · 17 years ago
  71. fb7373a Merge, from CGTUNE branch: by sewardj · 17 years ago
  72. e744153 Update copyright dates. by sewardj · 18 years ago
  73. dd40fdf by sewardj · 18 years ago
  74. aca070a Merge r1663-r1666: by sewardj · 18 years ago
  75. a33e9a4 Update copyright dates. by sewardj · 18 years ago
  76. 8f07359 Counterpart to r1605: in the ppc insn selector, don't use the bits by sewardj · 19 years ago
  77. a5f55da Don't use the bits VexArchInfo.hwcaps to distinguish ppc32 and ppc64, by sewardj · 19 years ago
  78. 3fd3967 Un-break ppc64 following recent hw-capabilities hackery. (sigh) by sewardj · 19 years ago
  79. 5117ce1 Change the way Vex represents architecture variants into something by sewardj · 19 years ago
  80. 9dd9cf1 Add Ijk_EmFail, a new kind of IR block exit: an emulation failure by sewardj · 19 years ago
  81. c716aea Two different sets of changes (hard to disentangle): by sewardj · 19 years ago
  82. ce02aa7 Merge in function wrapping support from the FNWRAP branch. That by sewardj · 19 years ago
  83. d0eae2d renamed VEX dirs guest-ppc32/ -> guest-ppc/, host-ppc32/ -> host-ppc/ by cerion · 19 years ago
  84. 5b2325f Changed naming convention from 'PPC32' to 'PPC' for all VEX code common to both PPC32 and PPC64. by cerion · 19 years ago
  85. 0528bb5 Modify amd64 backend to use jump-jump scheme rather than call-return scheme. by sewardj · 19 years ago
  86. 17c7f95 - x86 back end: change code generation convention, so that instead of by sewardj · 19 years ago
  87. f0de28c Implemented backend for ppc64, sharing ppc32 backend. by cerion · 19 years ago
  88. 92b6436 Added 'Bool mode64' to the various backend functions, to distinguish 32/64bit arch's. by cerion · 19 years ago
  89. f9517d0 Modify the tree builder to use a fixed-size binding environment rather by sewardj · 19 years ago
  90. 2d6b14a Use a very fast in-line allocator. This improves its performance by by sewardj · 19 years ago
  91. 059601a Revise the PPC32 subarchitecture kinds, so as to facilitated by sewardj · 19 years ago
  92. f461149 API change: pass both the VexGuestExtents and the original by sewardj · 19 years ago
  93. 6d26984 Track the status of the %EFLAGS.AC (alignment check) bit, but by sewardj · 19 years ago
  94. e74f6f7 Get rid of ludicrously over-paranoid assertion that caused all last by sewardj · 19 years ago
  95. 7bd6ffe by sewardj · 19 years ago
  96. dbcfae7 by sewardj · 19 years ago
  97. ec3c885 Make LibVEX_Translate (an API fn) take a Bool indicating whether or by sewardj · 19 years ago
  98. db4738a Basic support for self-checking translations. It fits quite neatly by sewardj · 19 years ago
  99. 9e6491a The logic that drove basic block to IR disassembly had been duplicated by sewardj · 19 years ago
  100. 27e1dd6 (API-visible change): generalise the VexSubArch idea. Everywhere by sewardj · 19 years ago