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gerrit-public.fairphone.software / platform / external / valgrind / 1fce8ded764751417136e07cc4637c6b4f6ddd77 / pub
  1. e971c6a Support the DCBZL instruction. Also, query the host CPU at startup by sewardj · 14 years ago
  2. 1f139f5 Add support for v6 media instructions in both ARM and Thumb modes. by sewardj · 14 years ago
  3. 2fdd416 Merge from branches/THUMB: new IR primops and associated by sewardj · 14 years ago
  4. ec0d9a0 Merge from branches/THUMB: hwcaps for ARM. May get simplified since by sewardj · 14 years ago
  5. d266447 Merge from branches/THUMB: front end changes to support: by sewardj · 14 years ago
  6. acfbd7d Add a moderately comprehensive implementation of the SSE4.2 string by sewardj · 14 years ago
  7. 0b2d3fe Add partial support for the SSE 4.2 PCMPISTRI instruction, at least by sewardj · 14 years ago
  8. 536fbab Only decode LZCNT if the host supports it, since otherwise we risk by sewardj · 14 years ago
  9. d15b597 Implement ROUNDSS (partial implementation, in the case where by sewardj · 14 years ago
  10. 69d98e3 Implement SSE4 instructions: PCMPGTQ PMAXUD PMINUD PMAXSB PMINSB PMULLD by sewardj · 14 years ago
  11. 752f906 Update copyright dates to 2010 and change license to standard GPL2+. by sewardj · 15 years ago
  12. 984d9b1 by sewardj · 15 years ago
  13. 6c299f3 Merge r1925:1948 from branches/ARM. This temporarily breaks all other by sewardj · 15 years ago
  14. e768e92 by sewardj · 15 years ago
  15. 3187dc7 Get rid of LibVEX_Version(). by sewardj · 15 years ago
  16. 1fb8c92 Add new integer comparison primitives Iop_CasCmp{EQ,NE}{8,16,32,64}, by sewardj · 15 years ago
  17. cef7d3e by sewardj · 15 years ago
  18. d652012 Double the size of the spill area. Fixes #195838. by sewardj · 15 years ago
  19. e9d8a26 Merge in branches/DCAS: by sewardj · 15 years ago
  20. 90472eb Make VexGuestAMD64State have a 16-aligned size once again, following r1886. by sewardj · 16 years ago
  21. e86310f In order to make it possible for Valgrind to restart client syscalls by sewardj · 16 years ago
  22. 2e28ac4 by sewardj · 16 years ago
  23. d660d41 Initial VEX-end support for Darwin (x86 and amd64). by sewardj · 16 years ago
  24. a203330 Add a description of the FP offset/size to type VexGuestLayout. by sewardj · 16 years ago
  25. 0f1ef86 Handle frin, frim, frip, friz, in 64-bit mode only, for now. by sewardj · 16 years ago
  26. c07349e Add support needed for exp-ptrcheck on ppc32/64. by sewardj · 16 years ago
  27. 019f406 Add Imbe_SnoopedStoreBegin and Imbe_SnoopedStoreEnd, to be used for by sewardj · 16 years ago
  28. 478646f Merge branches/OTRACK_BY_INSTRUMENTATION into the trunk. This by sewardj · 17 years ago
  29. a26d820 Update copyright dates ("200X-2007" --> "200X-2008"). by sewardj · 17 years ago
  30. d166e28 by sewardj · 17 years ago
  31. c4356f0 by sewardj · 17 years ago
  32. 0f50004 Support x86 $int 0x40 .. 0x43 instructions on Linux. Apparently these by sewardj · 17 years ago
  33. be1b6ff by sewardj · 17 years ago
  34. eb17e49 Merge from CGTUNE branch: by sewardj · 17 years ago
  35. 3465e75 Stop gcc-4.2 producing hundreds of complaints of the form "warning: by sewardj · 18 years ago
  36. f6c8ebf More IRBB -> IRSB renaming. by sewardj · 18 years ago
  37. fc1b541 Add 'missing' primop Iop_ReinterpF32asI32 and code generation support by sewardj · 18 years ago
  38. e744153 Update copyright dates. by sewardj · 18 years ago
  39. 78ec32b Add mkIRExprVec_6/7. by sewardj · 18 years ago
  40. d71ba83 x86 front end: Implement MASKMOVQ (MMX class insn, introduced in SSE1) by sewardj · 18 years ago
  41. dd40fdf by sewardj · 18 years ago
  42. 6f2f283 New function dopyIRBBExceptStmts which makes it a bit easier to write tools. by sewardj · 18 years ago
  43. 57c10c8 Add many extra comments describing the IR. by sewardj · 18 years ago
  44. aca070a Merge r1663-r1666: by sewardj · 18 years ago
  45. a33e9a4 Update copyright dates. by sewardj · 18 years ago
  46. f32d5a5 Add a function to set/clear the x86 carry flag. (untested) by sewardj · 19 years ago
  47. 21bd7c7 upmerge r1597 (ppc32 needs a lot of spill slots sometimes) by sewardj · 19 years ago
  48. 40c8026 Redo the way FP multiply-accumulate insns are done on ppc32/64. by sewardj · 19 years ago
  49. 334870d ppc32/64: handle twi/tdi (conditional trap) instructions by sewardj · 19 years ago
  50. f1b5b1a Followup to r1562: fixes for x86 by sewardj · 19 years ago
  51. b183b85 by sewardj · 19 years ago
  52. 5117ce1 Change the way Vex represents architecture variants into something by sewardj · 19 years ago
  53. baf971a Handle ppc32/64 fres, frsqrte. by sewardj · 19 years ago
  54. aa60ddf The ppc32 port ran itself out of spill slots on some heavy duty FP code. by sewardj · 19 years ago
  55. 5ff11dd More ppc64-only function wrapping hacks: by sewardj · 19 years ago
  56. 9dd9cf1 Add Ijk_EmFail, a new kind of IR block exit: an emulation failure by sewardj · 19 years ago
  57. c716aea Two different sets of changes (hard to disentangle): by sewardj · 19 years ago
  58. be482ae Give the ppc64 guest state a 16-entry pseudo-register array, by sewardj · 19 years ago
  59. ce02aa7 Merge in function wrapping support from the FNWRAP branch. That by sewardj · 19 years ago
  60. 7594920 Comment only changes - misc refs to ppc32 changed to ppc. by cerion · 19 years ago
  61. 5b2325f Changed naming convention from 'PPC32' to 'PPC' for all VEX code common to both PPC32 and PPC64. by cerion · 19 years ago
  62. 17c7f95 - x86 back end: change code generation convention, so that instead of by sewardj · 19 years ago
  63. f0de28c Implemented backend for ppc64, sharing ppc32 backend. by cerion · 19 years ago
  64. 7a3e39c fix padding for VexGuestPPC64State by cerion · 19 years ago
  65. 2831b00 Fixed a couple of mode32 bugs introduced by mode64 by cerion · 19 years ago
  66. dd56a48 Missed this in commit of vex: r1475 (ppc64 first pass) by cerion · 19 years ago
  67. d953ebb First pass at VEX support of ppc64. by cerion · 19 years ago
  68. 2d6b14a Use a very fast in-line allocator. This improves its performance by by sewardj · 19 years ago
  69. f294eb3 Yet more irops, for fp vector conversion/rounding. by cerion · 19 years ago
  70. bc5948e delete unused multiply primops by sewardj · 19 years ago
  71. 206c364 New irops: Iop_CmpGT32Fx4, Iop_CmpGE32Fx4 by cerion · 19 years ago
  72. 059601a Revise the PPC32 subarchitecture kinds, so as to facilitated by sewardj · 19 years ago
  73. 1bee561 Handle instrumentation artefacts arising from memchecking Altivec by sewardj · 19 years ago
  74. 24d06f1 Fix usage of Iop_MullEven* to give IR correct meaning of which lanes being multiplied, i.e. lowest significant lane = zero by cerion · 19 years ago
  75. 3f46a01 Simulate complete LDT and GDT, rather than just a prefix thereof. by sewardj · 19 years ago
  76. 1ac656a New irop Iop_MullEven* - a widening un/signed multiply of even lanes by cerion · 19 years ago
  77. 4fa325a API change: make the handling of syscall-denoting instructions a bit by sewardj · 19 years ago
  78. dc1f913 Fill in a few missing Altivec cases: by sewardj · 19 years ago
  79. f461149 API change: pass both the VexGuestExtents and the original by sewardj · 19 years ago
  80. 7355d27 Rename primop Iop_Rot* Iop_Rotl* by cerion · 19 years ago
  81. 2a4b845 Couple more primops: Iop_ShlN8x16, Iop_ShrN8x16, Iop_SarN8x16 by cerion · 19 years ago
  82. 9e7677b yet another new IR primop: Iop_QNarrow32Ux4 by cerion · 19 years ago
  83. f887b3e Added a number of new IR primops to support integer AltiVec insns by cerion · 19 years ago
  84. bd5cb07 ppc guest_state vector regs must be 16byte aligned for loads/stores by cerion · 19 years ago
  85. 225a034 by cerion · 19 years ago
  86. c4904af Don't emit cmovl since older x86s don't support it; instead emit a by sewardj · 19 years ago
  87. f07ed03 A minimal implementation of the x86 sysenter instruction by sewardj · 19 years ago
  88. 6d26984 Track the status of the %EFLAGS.AC (alignment check) bit, but by sewardj · 19 years ago
  89. 7787af4 - Partial implementation of reservations, to make lwarx/stwcx. work by sewardj · 19 years ago
  90. 7bd6ffe by sewardj · 19 years ago
  91. dbcfae7 by sewardj · 19 years ago
  92. b51f0f4 by sewardj · 19 years ago
  93. 900f6b5 Added LibVEX_GuestPPC32_put_cr7(), LibVEX_GuestPPC32_put_cr() by cerion · 19 years ago
  94. 51900a2 Added LibVEX_GuestPPC32_get_cr() for easy access to entire cond reg by cerion · 19 years ago
  95. c24824a Comment-only-change: record subtle interactions between self-checks by sewardj · 19 years ago
  96. 16a403b Tidy up some loose ends in the self-checking-translations machinery, by sewardj · 19 years ago
  97. ec3c885 Make LibVEX_Translate (an API fn) take a Bool indicating whether or by sewardj · 19 years ago
  98. db4738a Basic support for self-checking translations. It fits quite neatly by sewardj · 19 years ago
  99. b66dfa3 comment-only change: renumber register offsets correctly by cerion · 19 years ago
  100. af1ceca Enhance IR so as to distinguish between little- and big-endian loads and by sewardj · 19 years ago