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gerrit-public.fairphone.software / platform / external / valgrind / 5f438dd73072211989c6d496845bdc9b777ecbec / priv
  1. 5f438dd Rename and rationalise the vector narrowing and widening primops, so by sewardj · 13 years ago
  2. 718305c Unbreak Altivec support following r2159 (rename of saturating narrowing primops) by sewardj · 13 years ago
  3. 2260b99 Implement PACKUSDW (SSE4.1). Fixes #274776. by sewardj · 13 years ago
  4. c9bff7d Partially fix underspecification of saturating narrowing primops that by sewardj · 13 years ago
  5. bc161a4 Change the interface to LibVEX_Translate slightly, so as to make the by sewardj · 13 years ago
  6. e430418 Add some more spec rules, for performance purposes: by sewardj · 13 years ago
  7. 9cc2bbf Improvements to code generation for 32 bit instructions. When by sewardj · 13 years ago
  8. 010ac54 x86 and amd64 back ends: when generating transfers back to the by sewardj · 13 years ago
  9. 2f10aa6 Add a field 'UChar delta' to IRStmt_IMark, and use it to carry around by sewardj · 13 years ago
  10. 1e5fea6 s390x: provide clock instructions like STCK by sewardj · 13 years ago
  11. 3176386 ARM front end only: when processing Thumb instructions, create by sewardj · 13 years ago
  12. 7ee9752 Add LIKELY/UNLIKELY macros for general use, replacing s390x-specific by sewardj · 13 years ago
  13. cd2b025 s390x: fix DISP20 macro. Remove duplicate defn and avoid problems of by sewardj · 13 years ago
  14. 7d810d7 Handle Iop_I64UtoF32 in the ppc32/ppc64 insn selector. Fixes #270851. by sewardj · 13 years ago
  15. b3a860f Fix jump kind for indirect BLX for Thumb insns. Bug 266035 comment by sewardj · 13 years ago
  16. 5bb6ca2 Support DMB and DSB variants on Thumb. Bug 266035 comment 6. by sewardj · 13 years ago
  17. 54d75f7 Fix an assertion failure caused by r2144 (improved assertions to do by sewardj · 13 years ago
  18. 7e30807 Tighten up condition code handling in the back end, so as to placate by sewardj · 13 years ago
  19. e407ced Support DMB and DSB variants on ARM. Bug 266035 comment 3. by sewardj · 13 years ago
  20. f6d2cf9 Fix a bogus assertion observed by Florian Krohm. by sewardj · 13 years ago
  21. 13f12a5 Fix a nonsensical assertion observed by Florian Krohm. by sewardj · 13 years ago
  22. 99ff620 Add a spec rule for V after SUB. by sewardj · 13 years ago
  23. 3c14925 Split up armg_calculate_flags_nzcv into four functions that compute by sewardj · 13 years ago
  24. bb8b394 Improvements to condition code handling on ARM. by sewardj · 13 years ago
  25. d5436ce When simplifying (improving) the IR generated by the ARM front end, do by sewardj · 13 years ago
  26. d34e449 Handle Iop_Not64 when doing 32-bit code generation. Also, assert that by sewardj · 13 years ago
  27. 6900702 s390x : misc cleanups by sewardj · 13 years ago
  28. a52e37e s390x: Implement Ist_MBE by sewardj · 13 years ago
  29. a970c40 s390x: fix code confusion by sewardj · 13 years ago
  30. e0dd77e s390x: invalid use of R0 as base register by sewardj · 13 years ago
  31. d07b856 s390x: fpr - gpr transfer facility by sewardj · 13 years ago
  32. 95d6f3a Fix up incorrect usage of Iop_I64UtoF32 in the PowerPC front and back by sewardj · 13 years ago
  33. cb9ad0d Fix up some enum confusion to do with ARMNeonUnOp and ARMNeonUnOpS, as by sewardj · 13 years ago
  34. e522d4b Fix up enum confusion between PPCAvOp and PPCAvFpOp, as found by by sewardj · 13 years ago
  35. 66d5ef2 Add support for IBM Power ISA 2.06 -- stage 1. Bug #267630 and by sewardj · 13 years ago
  36. 652b56a s390x: reconsider "long displacement" requirement. We currently by sewardj · 13 years ago
  37. 15469da s390x: Make sure to point the PSW address to the next address on SIGILL by sewardj · 13 years ago
  38. b13a92a s390x: minor code generation tweaks. There were a few loose ends by sewardj · 13 years ago
  39. f74c86f s390x: tweak s390_emit_load_cc. #269864. (Florian Krohm, britzel@acm.org) by sewardj · 13 years ago
  40. 3c49aaa Remove unused parameter in functions s390_emit_SLL/SRL/SRA. by sewardj · 13 years ago
  41. d7bde72 Support conditional load and store for s390x (VEX side). by sewardj · 13 years ago
  42. 7f6330d Add some extra folding rules. Fixes #268513. (Florian Krohm <britzel@acm.org>) by sewardj · 13 years ago
  43. 06122e7 Remove dead assignments that gcc-4.6.0 complains about by sewardj · 13 years ago
  44. a6d0809 Add a spec rule for NS after LOGICB. Fixes #266990. by sewardj · 13 years ago
  45. 17b0e21 Don't overwrite CC_NDEP in shift by zero. Fixes #269354. by sewardj · 13 years ago
  46. 15c0104 Handle more cases of SUB (SP minus immediate/register). Also by sewardj · 13 years ago
  47. eae8db5 s390x: MHY is not universally available. Fixes #268930. by sewardj · 13 years ago
  48. 611b06e s390x: FLOGR is not universally available. Fixes #268715. by sewardj · 13 years ago
  49. b63967e s390x: improve IR generation for XC. Fixes #268621. by sewardj · 13 years ago
  50. 7cf5bd0 Emit Ain_Imm64 (64-bit immediate constant loads to register) using a by sewardj · 13 years ago
  51. 9d31dfd Fix some signed-vs-unsigned char warnings in s390 code. (Christian by sewardj · 13 years ago
  52. 03d9114 Wrap up "__attribute__((regparm(n)))" inside a macro so it is only by sewardj · 13 years ago
  53. 4cba9f4 Add folding rules for Clz32 and Clz64. See bug 243404 comment 52. by sewardj · 13 years ago
  54. 2019a97 Add a port to IBM z/Architecture (s390x) running Linux -- VEX by sewardj · 13 years ago
  55. d2b1816 Handle Ico_V128(0xFFFF), created by more aggressive constant folding by sewardj · 13 years ago
  56. ed75a68 Handle moves from TPIDRURO to integer registers in Thumb mode. by sewardj · 13 years ago
  57. 4d47547 Get rid of unintended complex integral constant, that causes build by sewardj · 14 years ago
  58. 2b9b43c Implement LOOPNEL (32-bit version of LOOPNE). Fixes #256669. by sewardj · 14 years ago
  59. 5556e5e Implement rex.W/FXSAVE and also both variants of FXRSTOR. by sewardj · 14 years ago
  60. ec993de Add alignment checking for FXSAVE/FXRSTOR. by sewardj · 14 years ago
  61. 186f869 Add support for SSE4.2 CRC32{B,W,L,Q}. Fixes #261966. by sewardj · 14 years ago
  62. 16b60e5 Accept redundant REX.W for EXTRACTPS. See #258870 comment 5. by sewardj · 14 years ago
  63. d59d92f Handle PCMPxSTRx $0x00. Fixes #262995. by sewardj · 14 years ago
  64. 11eeb84 Tolerate redundant REX.W in POPQ m64. (#256669). by sewardj · 14 years ago
  65. 321bbbf Add support for AAD and AAM (base 10 only). Fixes #256387. by sewardj · 14 years ago
  66. a42c6c6 Print 8 insn bytes when failing, not 6. by sewardj · 14 years ago
  67. 0874bee Implement SSE4.x EXTRACTPS. Fixes #258870. by sewardj · 14 years ago
  68. e9fd86c Implement SSE4.1 PBLENDW. Fixes #257011 (comment 1, at least). by sewardj · 14 years ago
  69. 815de0c Handle non-immediate-rounding-mode versions of ROUND{P,S}{S,D}. Fixes #255418. by sewardj · 14 years ago
  70. 28d672a Fix bug in ppc64g_dirtyhelper_LVS (well, elsewhere, really) causing by sewardj · 14 years ago
  71. 2770939 Implement ROUNDPD and ROUNDPS (imm rounding mode only). by sewardj · 14 years ago
  72. 50d89bf Save an instruction on the normal idiom generated for smc-checks. by sewardj · 14 years ago
  73. d6c1725 Improve performance of smc-checks substantially, by: by sewardj · 14 years ago
  74. 310d6b2 Add support for SMSAD{X}, SMLSD{X}, USAD{A}8. by sewardj · 14 years ago
  75. 64733c4 Update copyright notices. by sewardj · 14 years ago
  76. 646bc00 Handle NOP.W (Thumb) and NOP (ARM). Partial fix for #253636. by sewardj · 14 years ago
  77. 774b88b Fix bogus register constraints for ARM mode LDREX and STREX. by sewardj · 14 years ago
  78. b0d80ea NEON front end: fix bugs in VMIN, VZIP, VRSHL. by sewardj · 14 years ago
  79. 6aa87a6 Fix some enum type confusion in host_arm_defs.[ch]. by sewardj · 14 years ago
  80. a002def Thumb instructions: instead of generating tons of lardy boilerplate IR by sewardj · 14 years ago
  81. b48eddb Give all the ARM code generation enums non-overlapping value ranges, so by sewardj · 14 years ago
  82. 64d776c Improve constant folding of expressions of the form 'op(t,t)' by sewardj · 14 years ago
  83. 45ca0b9 Add alignment checks to MOVDQA and a bunch of other SSE insns which by sewardj · 14 years ago
  84. 33ca4ac Handle the undocumented but apparently-actually-used instruction by sewardj · 14 years ago
  85. eee6f3e amd64 CPUID: don't claim that the guest supports AES insns, by sewardj · 14 years ago
  86. e165a8a Increase the size of the JIT's scratch working area from 4MB to 5MB. by sewardj · 14 years ago
  87. 5de202d On ARM, request precise exceptions for R7. This is needed to by sewardj · 14 years ago
  88. 1a179b5 Support PCLMULDQ (Emmanuel Thomé, Emmanuel.Thome@gmail.com). Fixes #251251. by sewardj · 14 years ago
  89. 5e120aa Track (but ignore) the state of %RFLAGS.ACFLAG, since that is by sewardj · 14 years ago
  90. 7666c15 Handle Ity_I128 in sizeofIRType. (Florian Krohm, britzel@acm.org). by sewardj · 14 years ago
  91. 32feb4a Support CMPXCHG reg, reg on amd64. (Vince Weaver, vince@csl.cornell.edu). by sewardj · 14 years ago
  92. 48dc409 Handle ADC Iv, eAX and SBB Iv, eAX (Jakub Jelinek, jakub@redhat.com) by sewardj · 14 years ago
  93. 27312d3 by sewardj · 14 years ago
  94. 04d6da3 Implement (Thumb) ORN (immediate) and ORN (register). Fixes #252326. by sewardj · 14 years ago
  95. 4aec376 Implement v7 barrier insns (DMB, DSB, ISB) in Thumb mode by sewardj · 14 years ago
  96. e1a9396 Implement LDREX and STREX in Thumb mode. Fixes #252258. by sewardj · 14 years ago
  97. 389239a Implement RBIT in ARM mode. by sewardj · 14 years ago
  98. 854cc2b LibVEX_GuestARM_get_cpsr: set CPSR.Q, .GE, .T and .M by sewardj · 14 years ago
  99. db1c20a Implement (ARM): REV, REV16, SMMUL. by sewardj · 14 years ago
  100. ebba9ee Fix incorrect handling of VTRN.32 insn. (Dmitry Zhurikhin, zhur@ispras.ru) by sewardj · 14 years ago