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gerrit-public.fairphone.software / platform / external / valgrind / 64733c4c3f7e62054293d53ef0ac0ca9fd60d36f
  1. 64733c4 Update copyright notices. by sewardj · 14 years ago
  2. 646bc00 Handle NOP.W (Thumb) and NOP (ARM). Partial fix for #253636. by sewardj · 14 years ago
  3. 774b88b Fix bogus register constraints for ARM mode LDREX and STREX. by sewardj · 14 years ago
  4. b0d80ea NEON front end: fix bugs in VMIN, VZIP, VRSHL. by sewardj · 14 years ago
  5. 6aa87a6 Fix some enum type confusion in host_arm_defs.[ch]. by sewardj · 14 years ago
  6. a002def Thumb instructions: instead of generating tons of lardy boilerplate IR by sewardj · 14 years ago
  7. b48eddb Give all the ARM code generation enums non-overlapping value ranges, so by sewardj · 14 years ago
  8. 64d776c Improve constant folding of expressions of the form 'op(t,t)' by sewardj · 14 years ago
  9. 45ca0b9 Add alignment checks to MOVDQA and a bunch of other SSE insns which by sewardj · 14 years ago
  10. 33ca4ac Handle the undocumented but apparently-actually-used instruction by sewardj · 14 years ago
  11. eee6f3e amd64 CPUID: don't claim that the guest supports AES insns, by sewardj · 14 years ago
  12. eee3960 Comment-only change. by sewardj · 14 years ago
  13. e165a8a Increase the size of the JIT's scratch working area from 4MB to 5MB. by sewardj · 14 years ago
  14. 5de202d On ARM, request precise exceptions for R7. This is needed to by sewardj · 14 years ago
  15. 1a179b5 Support PCLMULDQ (Emmanuel Thomé, Emmanuel.Thome@gmail.com). Fixes #251251. by sewardj · 14 years ago
  16. 5e120aa Track (but ignore) the state of %RFLAGS.ACFLAG, since that is by sewardj · 14 years ago
  17. 7666c15 Handle Ity_I128 in sizeofIRType. (Florian Krohm, britzel@acm.org). by sewardj · 14 years ago
  18. 32feb4a Support CMPXCHG reg, reg on amd64. (Vince Weaver, vince@csl.cornell.edu). by sewardj · 14 years ago
  19. 48dc409 Handle ADC Iv, eAX and SBB Iv, eAX (Jakub Jelinek, jakub@redhat.com) by sewardj · 14 years ago
  20. 27312d3 by sewardj · 14 years ago
  21. 04d6da3 Implement (Thumb) ORN (immediate) and ORN (register). Fixes #252326. by sewardj · 14 years ago
  22. 4aec376 Implement v7 barrier insns (DMB, DSB, ISB) in Thumb mode by sewardj · 14 years ago
  23. e1a9396 Implement LDREX and STREX in Thumb mode. Fixes #252258. by sewardj · 14 years ago
  24. 389239a Implement RBIT in ARM mode. by sewardj · 14 years ago
  25. 854cc2b LibVEX_GuestARM_get_cpsr: set CPSR.Q, .GE, .T and .M by sewardj · 14 years ago
  26. db1c20a Implement (ARM): REV, REV16, SMMUL. by sewardj · 14 years ago
  27. ebba9ee Fix incorrect handling of VTRN.32 insn. (Dmitry Zhurikhin, zhur@ispras.ru) by sewardj · 14 years ago
  28. 93ba93f by sewardj · 14 years ago
  29. e2ea176 by sewardj · 14 years ago
  30. 21037f0 Implement UHADD8. by sewardj · 14 years ago
  31. 622b2d7 Implement SSUB8. by sewardj · 14 years ago
  32. 9aa5b04 In ARM mode: enable LDRD/STRD of the form "reg, [reg], reg" by sewardj · 14 years ago
  33. 22ac596 Implement SADD16, SSUB16, SASX, SMLAWB, SMLAWT. by sewardj · 14 years ago
  34. 1fce8de If the host does not support Neon, then don't accept Neon instructions by sewardj · 14 years ago
  35. cc85558 Handle 16Uto64, which can now show up at the back end as a by sewardj · 14 years ago
  36. ca257bc Minor amd64 instruction selection improvements, leading to a by sewardj · 14 years ago
  37. 7e84630 Support new PowerISA_2.05 instructions available on Power6 CPUs. by sewardj · 14 years ago
  38. e971c6a Support the DCBZL instruction. Also, query the host CPU at startup by sewardj · 14 years ago
  39. 8e074cc Enable BX PC in Thumb mode. Partial fix for #249775. by sewardj · 14 years ago
  40. 677e5af Handle RBIT (bit-reverse) in Thumb mode. Partial fix for #249924. by sewardj · 14 years ago
  41. e30973c Avoid genSpill/genReload asserts for VFP spills/reloads with offsets by sewardj · 14 years ago
  42. ef9ef37 Reduce to 5 the number of available Q (128-bit) registers available by sewardj · 14 years ago
  43. 4c3839e Support the PLI instruction (icache preload hint) in ARM mode, so by sewardj · 14 years ago
  44. 17bf0aa Fix debug printing for Neon VLDn/VSTn instructions. by sewardj · 14 years ago
  45. 21eaf24 Fix generation of writeback values in Neon VLDn/VSTn instructions. by sewardj · 14 years ago
  46. 1f139f5 Add support for v6 media instructions in both ARM and Thumb modes. by sewardj · 14 years ago
  47. c070405 Handle "Special" instructions in Thumb mode: "R3 = guest_NRADDR" and by sewardj · 14 years ago
  48. df86f16 Fix some compiler complaints when building on 64-bit platforms. by sewardj · 14 years ago
  49. 9dbbd7b Fix various compiler warnings and remove an unused function. by sewardj · 14 years ago
  50. 2fdd416 Merge from branches/THUMB: new IR primops and associated by sewardj · 14 years ago
  51. ec0d9a0 Merge from branches/THUMB: hwcaps for ARM. May get simplified since by sewardj · 14 years ago
  52. 6c60b32 Merge from branches/THUMB: back end changes to support NEON code generation. by sewardj · 14 years ago
  53. d266447 Merge from branches/THUMB: front end changes to support: by sewardj · 14 years ago
  54. be91791 Merge from branches/THUMB: A spechelper interface change that allows by sewardj · 14 years ago
  55. b54152a Enable SSE 4.1 and 4.2 by default on x86_64. (x86 remains stuck by sewardj · 14 years ago
  56. acfbd7d Add a moderately comprehensive implementation of the SSE4.2 string by sewardj · 14 years ago
  57. 0b2d3fe Add partial support for the SSE 4.2 PCMPISTRI instruction, at least by sewardj · 14 years ago
  58. 3d73810 Update for Core iX. by sewardj · 14 years ago
  59. 0283430 Don't trash the ELF ABI redzone for amd64 when emulating BT{,S,R,C} by sewardj · 14 years ago
  60. 287e9bb Add a folding rule for 32Sto64. by sewardj · 14 years ago
  61. 536fbab Only decode LZCNT if the host supports it, since otherwise we risk by sewardj · 14 years ago
  62. 9a660ea Support the amd SSE4.something LZCNT instruction. Fixes #212335 by sewardj · 14 years ago
  63. 57b0ba5 Handle mov[ua[pd G(xmm) -> E(xmm) case, which is something binutils by sewardj · 14 years ago
  64. 772f6df x86/amd64 FXTRACT: mimic the Core i5 behaviour when the argument is a by sewardj · 14 years ago
  65. 0fb6994 Ignore a redundant REX.W prefix on an MMX pinsrw instruction by sewardj · 14 years ago
  66. 95aa910 Add a program for printing out cpuid info. by sewardj · 14 years ago
  67. b727161 Support the SSE4 insn 'roundss' in 32-bit mode. Lack of this was by sewardj · 14 years ago
  68. d15b597 Implement ROUNDSS (partial implementation, in the case where by sewardj · 14 years ago
  69. 39aefda Implement ROUNDSD (partial implementation, in the case where by sewardj · 14 years ago
  70. 69d98e3 Implement SSE4 instructions: PCMPGTQ PMAXUD PMINUD PMAXSB PMINSB PMULLD by sewardj · 14 years ago
  71. fd18128 Implement more SSE4 instructions: PINSRD PMINUD POPCNTW POPCNTL POPCNTQ by sewardj · 14 years ago
  72. b9dc243 Implement SIDT and SGDT as pass-throughs to the host. It's a pretty by sewardj · 14 years ago
  73. c2433a8 Implement XADD reg,reg (Nicolas Sauzede, nicolas.sauzede@st.com). Fixes #195662. by sewardj · 14 years ago
  74. 9f5c8fd Enable FISTS. Fixes #234037. (Bradley Baetz, bbaetz@gmail.com) by sewardj · 14 years ago
  75. 412098c Handle v7 memory fence instructions: ISB DSB DMB and their v6 equivalents: by sewardj · 14 years ago
  76. deceef8 Handle more x86 NOP forms, as required by Fedora 13. Fixes bug by sewardj · 14 years ago
  77. 752f906 Update copyright dates to 2010 and change license to standard GPL2+. by sewardj · 14 years ago
  78. 2febc60 (re-commit r1976): Added new SSE4.1 instruction: PMAXUD by sewardj · 14 years ago
  79. e53a5e0 (re-commit r1975): Added new SSE4.1 instruction: PINSRQ by sewardj · 14 years ago
  80. 38523e9 (re-commit r1974): Fix up printing for some of the SSE4.1 insns. by sewardj · 14 years ago
  81. e76895d (re-commit r1973): by sewardj · 14 years ago
  82. 4342831 (re-commit r1972): Fixed copy+paste error in R1971 by sewardj · 14 years ago
  83. 733d589 (re-commit r1971) Added new SSE4 instructions PMINSD, PMAXSD. by sewardj · 14 years ago
  84. a1c1d9a (re-commit r1970): Tested BLENDPS Added new SSE4 instructions DPPD and DPPS by sewardj · 14 years ago
  85. d403e79 iselVecExpr_wrk: 128-bit constants: handle all 16 cases by de · 14 years ago
  86. b5afdbd Added new SSE4 instruction BLENDPS (backend needs a fix before testing) by de · 14 years ago
  87. 7cfc306 Enable PMOVSXBW and fix lane shift widths. by sewardj · 14 years ago
  88. 9ba870d Handle a few more cases in 128-bit constant generation, needed by by sewardj · 14 years ago
  89. 5a70f5c by de · 14 years ago
  90. 04ac5de Support FTOUIS, UXTAB, SXTAH. by sewardj · 14 years ago
  91. f7d3b2e Handle SBB Eb,Gb. by sewardj · 14 years ago
  92. 4df975f Fix incorrect spec rule for LE after INCB, for end-of range cases (arg = 0x7F). by sewardj · 14 years ago
  93. 30a20e9 CVTPI2PD (which converts 2 x I32 in M64 or MMX to 2 x F64 in XMM): by sewardj · 14 years ago
  94. 9581906 Majorly improved implementation of self-checking for translations. by sewardj · 14 years ago
  95. 0d925b1 x86/amd64 front ends: don't chase a conditional branch that leads by sewardj · 14 years ago
  96. 82f5688 Enable (optionally) chasing through conditional branches during trace by sewardj · 14 years ago
  97. 984d9b1 by sewardj · 14 years ago
  98. ff6b34a amd64: add a couple more spec cases: NLE after SUBL, and NZ after LOGICB. by sewardj · 14 years ago
  99. ef425db For 32-bit reads of integer guest registers, generate a 64-bit Get by sewardj · 15 years ago
  100. 80bea7b * support PLD (cache-preload-hint) instructions by sewardj · 15 years ago