- 8b1715b Whitespace-only change: restrict to 80 col width. by sewardj · 11 years ago
- 1df406c mips64: Change the initial value of fpu registers. by dejanj · 11 years ago
- 6068788 arm64: rename guest_SP to guest_XSP so as to avoid a name clash with by sewardj · 11 years ago
- aeeb31d Add missing ULLs to some 64-bit immediates. by sewardj · 11 years ago
- bbcf188 Add support for ARMv8 AArch64 (the 64 bit ARM instruction set): by sewardj · 11 years ago
- 0e457fc LibVEX_GuestAMD64_initialise(): give an initial value for by sewardj · 11 years ago
- a2039c5 The result of rounding a 128-bit BFP/DFP value to 32/64 bit needs to by florian · 11 years ago
- d5453bf Bug 328100 - XABORT not implemented. by mjw · 11 years ago
- 4183322 mips32/64: Fixed the problem with fpu instructions. by dejanj · 11 years ago
- e03b600 Fix Bug 327284. The condition code of risbg was not correct. by cborntra · 11 years ago
- 781f1bd mips32: Fix problem with some mips32 dsp instructions. by dejanj · 11 years ago
- a445f1b mips32: Fixed the problem with FCSR register. by dejanj · 11 years ago
- f5530ec In 64 bit mode, allow 64 bit return values from clean helper calls. by sewardj · 11 years ago
- 89ae847 Update copyright dates (20XY-2012 ==> 20XY-2013) by sewardj · 11 years ago
- 83da6d7 Handle PCMPxSTRx cases 0x30 and 0x40. Fixes #320998. by sewardj · 11 years ago
- 60c6bac This commit adds support for the following instructions: by carll · 11 years ago
- 7deaf95 Power 8 support, phase 5 by carll · 11 years ago
- 6491f86 Tidyup -- no functional change. Replace all "pfx & PFX_LOCK" by sewardj · 11 years ago
- 38b1d69 amd64 front end: accept XACQUIRE and XRELEASE on exactly the insns that by sewardj · 11 years ago
- 66e40ae Add support for an alternative encoding of 'PUSH reg', viz FF /6, by sewardj · 11 years ago
- 2691a61 PPC32/64: Allow 16 byte icache lines. by sewardj · 11 years ago
- fcce5f8 Power PC, add the two privileged Transactional Memory instructions. by carll · 11 years ago
- 3bc88cc mips64: add extra Iop cases in VEX. by dejanj · 11 years ago
- 9d690c6 Fix guest_amd64_toIR xbegin and xtest to match cpuid given for AVX hwcaps. by mjw · 11 years ago
- 6c758b6 Phase 4 support for IBM Power ISA 2.07 by carll · 11 years ago
- 8943d02 Power PC, Approach 1, add Transactional Memory instruction support by carll · 11 years ago
- 48ae46b Phase 3 support for IBM Power ISA 2.07 by carll · 11 years ago
- 4ccd258 Implement LDRHT (Thumb), LDRSHT (Thumb), [LDR,ST]{S}[B,H]T (ARM). by sewardj · 11 years ago
- 3b22fc8 Implement LDRHT (Thumb), LDRSHT (Thumb), [LDR,ST]{S}[B,H]T (ARM). by sewardj · 11 years ago
- 9e4c376 Add a kludgey implementation of XTEST to go with the kludgey by sewardj · 11 years ago
- f7e5958 armg_calculate_condition: add missing masking (probably pointless, by sewardj · 11 years ago
- e8e46ab mips64: finetune mips_dirtyhelper_calculate_FCSR by petarj · 11 years ago
- 8e70cdc mips32: protect mips32r2 instructions with a flag by petarj · 11 years ago
- 1c56013 mips32/64: Save the value of FCSR register at the beginning and restore it by dejanj · 11 years ago
- a759d17 mips32/64: Code cleanup and VEX optimizations. No functional changes. by dejanj · 11 years ago
- 512f059 mips32/64: Fix the problem with dirty helper when the by dejanj · 11 years ago
- a56f369 Add support for the Intel TM "xbegin" instruction, by jumping directly by sewardj · 11 years ago
- 1bf44e3 x86 front ends: tighten up decoding of MOV Ib,Eb and MOV Iv,Ev. This by sewardj · 11 years ago
- aae16ca Unbreak the build on non-MIPS platforms. by tom · 11 years ago
- 8007ea6 mips32/mips64: additional VEX support for FCSR register. by dejanj · 11 years ago
- 5cc3b45 mips64: VEX support for MIPS64 Octeon Instructions by petarj · 11 years ago
- bc7d6f4 mips: clean-up in hardware detection (Cavium/DSP ASEs) by petarj · 11 years ago
- 994cc46 mips32: small cleanup in show_hwcaps_mips32 by petarj · 11 years ago
- af514c0 s390: Add spechelper for s390_calculate_cc. by florian · 11 years ago
- c31e6cb Bug 323893 - SSE3 not available on amd cpus in valgrind. by mjw · 11 years ago
- 6fef87a The Power ISA 2.07 document includes a correction to the description for the by carll · 11 years ago
- d6bc217 Remove dead code. by florian · 11 years ago
- 740da72 Enhance ado_treebuild_BB to allow an expression preceding a Put by florian · 11 years ago
- 81d4ff2 mips64: fixed problem with Iop's for mips64. by dejanj · 11 years ago
- 78850ae Bugzilla 323437, this is phase 2 in a series of patches adding support for IBM by carll · 11 years ago
- de6f710 Add a few more optimisations for CmpwNEZ64, CmpNEZ32, and CmpNEZ64. by florian · 11 years ago
- 38b79ac The existing overflow detection in VEX/priv/guest_ppc_toIR.c/set_XER_OV_64() by carll · 11 years ago
- 9708b6a The patch used the binary constants 0b10000 and 0b10001. The 0b designator by carll · 11 years ago
- c3a3791 Update list of ignored files. by florian · 11 years ago
- b77db0e The current code is not properly handling a non-zero TH field in the by carll · 11 years ago
- 2accb5e deltaIRExpr cannot handle Iex_VECRET and Iex_BBPTR and needs to be guarded. by florian · 11 years ago
- e3a103f mips32/mips64: Fix the problem with lwl and lwr for mips32 and mips64. by dejanj · 11 years ago
- 54eea4e Comment-only change. by sewardj · 11 years ago
- 854912a Add an optimisation for Iop_Left64. by florian · 11 years ago
- 55ce7b7 Add algebraic simplifications for Iop_And64 (same as for Iop_And32). by florian · 11 years ago
- 6c65c12 Support mmxext (integer sse) subset on i386 (athlon). by mjw · 11 years ago
- d69cd9a mips64: Fix a problem with CCall.retty type. by dejanj · 11 years ago
- 82cc37c Add support for 256-bit return values for dirty helpers (amd64 only). by sewardj · 11 years ago
- 9041956 Eliminate IRExprP__VECRET and IRExprP__BBPTR and introduce two new by florian · 11 years ago
- c529555 mips32/mips64: Fix compiler warnings. by dejanj · 11 years ago
- 0c74bb5 Initial ISA 2.07 support for POWER8-tuned libc by carll · 11 years ago
- 74142b8 Add infrastructural support (IR, VEX) to allow returns of 128- by sewardj · 11 years ago
- 3cfd1f0 Add a spec rule for SUBQ/NLE. by sewardj · 11 years ago
- 0af77fc Update Makefile-gcc to include additional files that were added in r2702. by florian · 11 years ago
- befee0b Do not use the 0b notation as older GCC's do not accept it. by florian · 11 years ago
- 9138b17 Rename ppc_cache_line_szB to indicate that this is the size by florian · 11 years ago
- 9875715 mips32: Correctly model SHLL_S.PH on MIPS32. by dejanj · 11 years ago
- 1bdaac5 s390: New machine model: zBC12 by florian · 11 years ago
- c3fee0d mips32: Add support for mips32 DSP instruction set. by dejanj · 11 years ago
- a325ee1 by sewardj · 11 years ago
- 6ed5c34 Add support for by sewardj · 11 years ago
- a8e327d mips: implement Iop_8Uto64 in iselInt64Expr by petarj · 11 years ago
- 7ab421d s390: Support some more BFP <-> DFP conversions (the ones by florian · 11 years ago
- b22838d Add some more IRops to convert between binary floating point and by florian · 11 years ago
- 70a2606 mips64: fix 'unused variable' warning by petarj · 11 years ago
- 79e5a48 Eliminate IRRoundingModeDFP by merging its values into IRRoundingMode. by florian · 11 years ago
- bafb826 s390x: Make the CC_DEP1 field appear completely initialised when by florian · 11 years ago
- ccd78cd mips32/mips64: implement sdl, sdr, swl and swr without reading memory by petarj · 11 years ago
- 80f674a Implement STRT. Fixes #319395. (Vasily Golubev, w.golubev@mail.ru) by sewardj · 11 years ago
- e660158 Implement SSAT16. Fixes #318929. (Vasily Golubev, w.golubev@mail.ru) by sewardj · 11 years ago
- c589228 Fix s390 build failure. Patch by Maran Pakkirisamy (maranp@linux.vnet.ibm.com). by florian · 11 years ago
- 78d5ef7 s390: First round of changes to support the PFPO insn. by florian · 11 years ago
- b40431f Get rid of gcc warning on non-MIPS platforms. by sewardj · 11 years ago
- 37c57f3 Add the following IROPs which are needed for s390 DFP support: by florian · 11 years ago
- 1fb1e34 mips: fix some style issues, non-functional change by petarj · 11 years ago
- bc3af3c mips: fix corner case for INS instruction by petarj · 11 years ago
- 92001d4 STRD (both ARM and Thumb): for push-like cases -- specifically, STRD by sewardj · 11 years ago
- ccff5f4 Implement SMMLA{r}, both ARM and Thumb. n-i-bz. by sewardj · 11 years ago
- f78a81c Generate better code for Shl64(x, imm8) since the Neon front end by sewardj · 11 years ago
- 0adc2f2 VLD4/VST4: generate in-line interleave/de-interleave code, so that by sewardj · 11 years ago
- c1e23c4 VLD3/VST3: generate in-line interleave/de-interleave code, so that by sewardj · 11 years ago
- 0c30de8 mips: fix endian issues for LWL, LWR, LDR and LDL for mips64 by petarj · 11 years ago
- 1df8096 Improved front end translations for Neon V{LD,ST}{1,2} instructions, by sewardj · 11 years ago
- de61a39 Remove some unused ifdeffery that allowed disabling QC flag updating for Neon. by sewardj · 11 years ago
- 8bde7f1 Implement ARM SDIV and UDIV instructions. Fixes #314178. Partially by sewardj · 11 years ago