- a97dddf arm64: implement: {uqshl, sqshl, sqshlu} (vector, imm). by sewardj · 10 years ago
- ecedd98 arm64: implement: by sewardj · 10 years ago
- 1297218 arm64: add support for: sqshl, uqshl, sqrshl, uqrshl (reg) (vector and scalar) by sewardj · 10 years ago
- 9b76916 Improve infrastructure for dealing with endianness in VEX. This patch by sewardj · 10 years ago
- 54ffa1d arm64: implement: by sewardj · 10 years ago
- 51d012a arm64: implement: sqneg, {u,s}q{add,sub} (scalar), by sewardj · 10 years ago
- 8e91fd4 arm64: implement: {sli,sri} (vector & scalar), sqabs (vector & scalar) by sewardj · 10 years ago
- a5a6b75 arm64: implement: sadalp uadalp saddlp uaddlp saddlv uaddlv saddw{2} by sewardj · 10 years ago
- 6f312d0 arm64: implement: sabal uabal sabdl uabdl saddl uaddl ssubl usubl by sewardj · 10 years ago
- df9d6d5 arm64: by sewardj · 10 years ago
- 715d162 arm64: implement: rbit 16b,8b, rev16 16b,8b by sewardj · 10 years ago
- 31b5a95 arm64: implement pmull{2}. by sewardj · 10 years ago
- 168c8bd arm64: implement: by sewardj · 10 years ago
- 76ac476 Increase the number of vector registers available for allocation from 3 to 5. by sewardj · 10 years ago
- ab33a7a Implement: dup_{d_d[], s_s[], h_h[], b_b[]}, ext by sewardj · 10 years ago
- 2b6fd5e Implement: orr_{8h,4h}_imm8_shifted, orr_{4s,2s}_imm8_shifted, by sewardj · 10 years ago
- 25523c4 arm64: implement: abs d_d, neg d_d, abs std7_std7, addhn, subhn, raddhn, rsubhn by sewardj · 10 years ago
- d96daf6 Remove temporary front end scaffolding for Cat{Even,Odd}Lanes by sewardj · 10 years ago
- 85fbb02 Implement FMUL 2d_2d_d[], 4s_4s_s[], 2s_2s_s[]. by sewardj · 10 years ago
- 7fce7cc Enable 'smulh'. by sewardj · 10 years ago
- 05f5e01 Renaming only (no functional change): rename IR artefacts to do by sewardj · 10 years ago
- 6590299 ARM64: add support for cache management instructions (VEX side): by sewardj · 10 years ago
- 9301343 Finish off vector integer comparison instructions, and by sewardj · 10 years ago
- 950ca7a Implement by sewardj · 10 years ago
- 92d0ae3 Implement TBL and TBX instructions. by sewardj · 10 years ago
- 2bd1ffe Implement FCM{EQ,GE,GT}, FAC{GE,GT} (vector). by sewardj · 10 years ago
- 505a27d Back-end handling of Iop_CmpNEZ32x4, Iop_CmpNEZ16x8, Iop_CmpNEZ8x16, by sewardj · 11 years ago
- 99c1f81 Implement a couple of backend artefacts needed by Memcheck on large by sewardj · 11 years ago
- 1eaaec2 Support extra instruction bits and pieces, enough to get Firefox started: by sewardj · 11 years ago
- 32d8675 Implement REV16, REV32, FCVTN, SHL (vector, immediate), NEG (vector) by sewardj · 11 years ago
- 9b1cf5e Select and emit insns for Iop_ZeroHI64ofV128 Iop_Max8Sx16 Iop_Min8Sx16 by sewardj · 11 years ago
- 7d00913 First pass at implementation of load/store exclusive and by sewardj · 11 years ago
- c6acaa4 Implement unchainXDirect_ARM64. by sewardj · 11 years ago
- e520bb3 Implement more aarch64 vector insns: by sewardj · 11 years ago
- fab0914 Implement more aarch64 vector insns: by sewardj · 11 years ago
- f5b0891 Implement a few more vector aarch64 insns: by sewardj · 11 years ago
- ecde697 Implement a few more vector aarch64 insns: by sewardj · 11 years ago
- 606c4ba Improve front and back end support for SIMD instructions on Arm64. by sewardj · 11 years ago
- bbcf188 Add support for ARMv8 AArch64 (the 64 bit ARM instruction set): by sewardj · 11 years ago