- ab9055b For SSE scalar comparison operations where one operand is in memory, by sewardj · 19 years ago
- b029a61 Apparently "sync" has an undocumented relative called "lwsync". Sigh. by sewardj · 19 years ago
- cb1f68e Handle dcbz in 64-bit mode. by sewardj · 19 years ago
- a9e4a80 Performance improvements for flag handling. by sewardj · 19 years ago
- dc12d39 Comment-only fix by sewardj · 19 years ago
- 7594920 Comment only changes - misc refs to ppc32 changed to ppc. by cerion · 19 years ago
- 4628ccd Put mode64 in ISelEnv, removing global variable. by cerion · 19 years ago
- fb197c4 Fix AltiVec load/store on ppc64 - was only considering lo32 bits of address. by cerion · 19 years ago
- 347da2c Handle 64HLto128 in 64-bit mode. by sewardj · 19 years ago
- d0eae2d renamed VEX dirs guest-ppc32/ -> guest-ppc/, host-ppc32/ -> host-ppc/ by cerion · 19 years ago
- a5e5f5f Update comment. by sewardj · 19 years ago
- 47bd753 Deal with backend case of 1Sto64 by cerion · 19 years ago
- 5b2325f Changed naming convention from 'PPC32' to 'PPC' for all VEX code common to both PPC32 and PPC64. by cerion · 19 years ago
- 07b07a9 Implemented almost all of the remaining 64bit-mode insns. by cerion · 19 years ago
- 09bbf50 small fixes for ppc64 layout stuff by sewardj · 19 years ago
- a162c2c Strict-aliasing fix needed to make gcc-4.1.0 happy. by sewardj · 19 years ago
- 59b2c31 Fix typos. by cerion · 19 years ago
- 8f53e99 Fix switchback.c to reflect changes to call of LibVEX_Translate() by cerion · 19 years ago
- bb01b7c Fixed up front and backend for 32bit mul,div,cmp,shift in mode64 by cerion · 19 years ago
- f774505 ppc32/64 backend: take r29 out of circulation so the Valgrind by sewardj · 19 years ago
- b8a8dba Make suitable changes for ppc32/ppc64 following recent x86/amd64 by sewardj · 19 years ago
- 0528bb5 Modify amd64 backend to use jump-jump scheme rather than call-return scheme. by sewardj · 19 years ago
- 17c7f95 - x86 back end: change code generation convention, so that instead of by sewardj · 19 years ago
- 18e3189 Stop gcc complaining. by sewardj · 19 years ago
- 876ef41 Enable fsqrt Document store fp single-precision problem by cerion · 19 years ago
- 9139119 More svn:ignores for VEX. by cerion · 19 years ago
- 6ded389 Switchbacker updates by cerion · 19 years ago
- 7d730cf Fix vex_printf padding. by cerion · 19 years ago
- f0de28c Implemented backend for ppc64, sharing ppc32 backend. by cerion · 19 years ago
- 92b6436 Added 'Bool mode64' to the various backend functions, to distinguish 32/64bit arch's. by cerion · 19 years ago
- 7a3e39c fix padding for VexGuestPPC64State by cerion · 19 years ago
- 729edb7 Re-enabled ppc32 frontend floating point load/store single precision insns: by cerion · 19 years ago
- 2831b00 Fixed a couple of mode32 bugs introduced by mode64 by cerion · 19 years ago
- df07b88 Fix %lr handling for bcctr and bclr. by sewardj · 19 years ago
- 5df65bb Set mode64 from the given guest subarch. by sewardj · 19 years ago
- dd56a48 Missed this in commit of vex: r1475 (ppc64 first pass) by cerion · 19 years ago
- d953ebb First pass at VEX support of ppc64. by cerion · 19 years ago
- f9517d0 Modify the tree builder to use a fixed-size binding environment rather by sewardj · 19 years ago
- ba97adb 3rd go at making args match format string. by sewardj · 19 years ago
- 66afb9f 64-bit format string fix by sewardj · 19 years ago
- 4eeda9c Be paranoid about the alignment of the storage arrays. by sewardj · 19 years ago
- 2d6b14a Use a very fast in-line allocator. This improves its performance by by sewardj · 19 years ago
- 2573c25 Compile vex at -O2. This improves its performance by about 15% by sewardj · 19 years ago
- 2ead522 Do float-to-bit-image conversion in a way which does not break ANSI C by sewardj · 19 years ago
- 41a7b70 gcc-2.96 build fixes by sewardj · 19 years ago
- edf7fc5 Cleaned up access to 'special purpose' registers. by cerion · 19 years ago
- 8f3bc90 Track valgrind r5196, wrt Non-Java mode by cerion · 19 years ago
- 76de5cf Cleaned up toIR.c somewhat by cerion · 19 years ago
- d963eb4 Implemented most of the remaining altivec fp ops: by cerion · 19 years ago
- f294eb3 Yet more irops, for fp vector conversion/rounding. by cerion · 19 years ago
- bfceb08 Implement SSE2 'clflush'. by sewardj · 19 years ago
- bc5948e delete unused multiply primops by sewardj · 19 years ago
- f7da610 gcc4 picked up a typo. by cerion · 19 years ago
- f3f173c More av insns: vmaddfp, vnmsubfp by cerion · 19 years ago
- 8ea0d3e Frontend by cerion · 19 years ago
- 206c364 New irops: Iop_CmpGT32Fx4, Iop_CmpGE32Fx4 by cerion · 19 years ago
- 77fd846 More profiling-induced speedups. by sewardj · 19 years ago
- 4b06a0b Add some flag-specialisation cases that profiling showed the need for. by sewardj · 19 years ago
- 059601a Revise the PPC32 subarchitecture kinds, so as to facilitated by sewardj · 19 years ago
- d37be03 Always mark blrl as a return. by sewardj · 19 years ago
- 88c5796 Add "make -j N" kludge to Vex too. by sewardj · 19 years ago
- 1bee561 Handle instrumentation artefacts arising from memchecking Altivec by sewardj · 19 years ago
- 24d06f1 Fix usage of Iop_MullEven* to give IR correct meaning of which lanes being multiplied, i.e. lowest significant lane = zero by cerion · 19 years ago
- 4a49b03 Frontend: by cerion · 19 years ago
- ccd0c84 Don't delete existing target-specific .a's when a target-switch happens. by sewardj · 19 years ago
- a1eb31c Changes for biarch (x86 and amd64) support. by sewardj · 19 years ago
- 90e91ee Handle some SSE3 instructions. A curious side-effect of this is that by sewardj · 19 years ago
- 3f46a01 Simulate complete LDT and GDT, rather than just a prefix thereof. by sewardj · 19 years ago
- 43f4573 format string wibble by sewardj · 19 years ago
- f526843 Stop gcc4 complaining. by sewardj · 19 years ago
- 0585a03 Implement FINIT. by sewardj · 19 years ago
- b928263 Implement vector FP unordered compares on amd64. by sewardj · 19 years ago
- a26f661 The earth's core is a vast mass of molten sse and sse2 instructions. by sewardj · 19 years ago
- 9fb2f47 Reenable FUCOMP %st(0),%st(?). by sewardj · 19 years ago
- 75ce365 Implement SHRDv imm8. by sewardj · 19 years ago
- 33ef9c2 Implement shld/shrd on amd64. Total timewasting nightmare, not helped by sewardj · 19 years ago
- 1ac656a New irop Iop_MullEven* - a widening un/signed multiply of even lanes by cerion · 19 years ago
- c01c1fa Handle jecxz in addition to jrcxz. by sewardj · 19 years ago
- 42561ef Handle address-size overrides in the common case (explicit memory references). by sewardj · 19 years ago
- 6d7c4f0 Handle any number of 0x66 (operand-size-override) prefixes. by sewardj · 19 years ago
- 5e55f49 wibble by sewardj · 19 years ago
- 4fa325a API change: make the handling of syscall-denoting instructions a bit by sewardj · 19 years ago
- 36e2355 Generate offsets for all amd64 integer registers. by sewardj · 19 years ago
- 240fd86 Implement 66 0F 11 = MOVUPD (untested) by sewardj · 19 years ago
- 62d0543 Tidy up a couple of format strings. by sewardj · 19 years ago
- d14c570 x86 front end: implement in/out insns. by sewardj · 19 years ago
- dc1f913 Fill in a few missing Altivec cases: by sewardj · 19 years ago
- 3f21fd3 Remove inefficient and not-completely-general logic in addHRegUse and by sewardj · 19 years ago
- d147094 Minor altivec changes: by sewardj · 19 years ago
- 69b7291 Unbreak build. by sewardj · 19 years ago
- f461149 API change: pass both the VexGuestExtents and the original by sewardj · 19 years ago
- 197bd17 Build fixes for gcc-2.96 (which does not allow declarations after the by sewardj · 19 years ago
- dfb1144 Handle the out-of-range shift cases for slw/srw in a different way by sewardj · 19 years ago
- 9d540e5 Enable chasing of unconditional branches and calls. by sewardj · 19 years ago
- 26b3320 Special-case rlwnms which are really slwi or srwi. This gives about by sewardj · 19 years ago
- fb6c179 Handle FUCOM %st(0),%st(?). by sewardj · 19 years ago
- a7690fb Handle BT/BTS/BTR/BTC at size 4 as well as 8. by sewardj · 19 years ago
- fdfa886 Implement JRCXZ. by sewardj · 19 years ago
- 59ff5d4 Handle the redundant-encoding (Grp5) versions of {inc,dec}{b,w}. by sewardj · 19 years ago
- b8a3dea Handle SSE2 pmaddwd. by sewardj · 19 years ago