1. d8c64e0 Constification part 5. by florian · 10 years ago
  2. 8462d11 Constification part 4. by florian · 10 years ago
  3. 7d6f81d Constification part 2. by florian · 10 years ago
  4. 9b76916 Improve infrastructure for dealing with endianness in VEX. This patch by sewardj · 10 years ago
  5. 6ced72b mips64: Support for Cavium MIPS Octeon Atomic and Count Instructions. by dejanj · 10 years ago
  6. 05f5e01 Renaming only (no functional change): rename IR artefacts to do by sewardj · 10 years ago
  7. f37c086 mips32: Fix the problem with the floating point compare instruction on mips32. by dejanj · 10 years ago
  8. 0e006f2 mips32: VEX Support for 64bit FPU on MIPS32 platforms. by dejanj · 10 years ago
  9. 781f1bd mips32: Fix problem with some mips32 dsp instructions. by dejanj · 11 years ago
  10. 3bc88cc mips64: add extra Iop cases in VEX. by dejanj · 11 years ago
  11. a759d17 mips32/64: Code cleanup and VEX optimizations. No functional changes. by dejanj · 11 years ago
  12. 74142b8 Add infrastructural support (IR, VEX) to allow returns of 128- by sewardj · 11 years ago
  13. c3fee0d mips32: Add support for mips32 DSP instruction set. by dejanj · 11 years ago
  14. 0c30de8 mips: fix endian issues for LWL, LWR, LDR and LDL for mips64 by petarj · 11 years ago
  15. b92a954 mips: adding MIPS64LE support to VEX by petarj · 11 years ago
  16. a81d9be mips: Fixing some HReg <--> UInt mixups spotted by Florian. by petarj · 11 years ago
  17. 4b5abc2 mips: fixing issues spotted by a static code analysis tool by petarj · 12 years ago
  18. cfe046e Merge, from branches/COMEM, revisions 2568 to 2641. by sewardj · 12 years ago
  19. 55085f8 Changes for -Wwrite-strings by florian · 12 years ago
  20. a6a1986 Add a proper support for several MIPS instructions that generate SigFPE. by petarj · 12 years ago
  21. 5df8ab0 Fix HChar / UCHar / Char mixups. VEX now compiles without by florian · 12 years ago
  22. 98f1170 Shorten the list of allocable registers for MIPS to fit Loongson MIPS32 mode. by petarj · 12 years ago
  23. 1ec43e0 Load/store doubles on MIPS are modeled through Ity_F64 rather than two Ity_F32. by petarj · 12 years ago
  24. 7fa6354 Remove redundant break statements. by florian · 12 years ago
  25. 362cf84 Merge in a port for mips32-linux, by Petar Jovanovic and Dejan Jevtic, by sewardj · 12 years ago