Gitiles
Code Review Sign In
gerrit-public.fairphone.software / platform / external / valgrind / ad00ea9f40f930d98bb2d278291a6c4c6636d6d6 / priv / host_x86_defs.c
  1. d8c64e0 Constification part 5. by florian · 10 years ago
  2. 8462d11 Constification part 4. by florian · 10 years ago
  3. 7d6f81d Constification part 2. by florian · 10 years ago
  4. 9b76916 Improve infrastructure for dealing with endianness in VEX. This patch by sewardj · 10 years ago
  5. 05f5e01 Renaming only (no functional change): rename IR artefacts to do by sewardj · 10 years ago
  6. e9c51c9 x87 instructions FSIN, FCOS, FSINCOS and FPTAN: handle out-of-range by sewardj · 10 years ago
  7. 89ae847 Update copyright dates (20XY-2012 ==> 20XY-2013) by sewardj · 11 years ago
  8. 6c65c12 Support mmxext (integer sse) subset on i386 (athlon). by mjw · 11 years ago
  9. 74142b8 Add infrastructural support (IR, VEX) to allow returns of 128- by sewardj · 11 years ago
  10. 79efdc6 Make HReg a struct. In the past there were several occurences where by florian · 11 years ago
  11. b5e7ced Fix some HReg/UInt mixups spotted by Florian. by sewardj · 11 years ago
  12. cfe046e Merge, from branches/COMEM, revisions 2568 to 2641. by sewardj · 12 years ago
  13. 55085f8 Changes for -Wwrite-strings by florian · 12 years ago
  14. 5ea257b Change the return value of LibVEX_{Chain,UnChain,PatchProfInc}. by florian · 12 years ago
  15. 25e5473 Update copyright dates to include 2012. by sewardj · 12 years ago
  16. 39aacda (post-tchain-merge cleanup): x86: handle a couple more syscall kinds by sewardj · 12 years ago
  17. c6f970f Add translation chaining support for amd64, x86 and ARM (VEX side). See #296422. by sewardj · 12 years ago
  18. e6c53e0 Update all copyright dates, from 20xy-2010 to 20xy-2011. by sewardj · 13 years ago
  19. 010ac54 x86 and amd64 back ends: when generating transfers back to the by sewardj · 13 years ago
  20. 536fbab Only decode LZCNT if the host supports it, since otherwise we risk by sewardj · 14 years ago
  21. 752f906 Update copyright dates to 2010 and change license to standard GPL2+. by sewardj · 14 years ago
  22. 2a1ed8e Make the x86 and amd64 back ends use the revised prototypes for by sewardj · 15 years ago
  23. 9e341ca Tell the register allocator on x86 that xmm0..7 are trashed across by sewardj · 15 years ago
  24. cef7d3e by sewardj · 15 years ago[Renamed (99%) from priv/host-x86/hdefs.c]
  25. e9d8a26 Merge in branches/DCAS: by sewardj · 15 years ago
  26. d660d41 Initial VEX-end support for Darwin (x86 and amd64). by sewardj · 16 years ago
  27. a26d820 Update copyright dates ("200X-2007" --> "200X-2008"). by sewardj · 16 years ago
  28. 0f50004 Support x86 $int 0x40 .. 0x43 instructions on Linux. Apparently these by sewardj · 17 years ago
  29. eb17e49 Merge from CGTUNE branch: by sewardj · 17 years ago
  30. fb7373a Merge, from CGTUNE branch: by sewardj · 17 years ago
  31. 79e04f8 Teach the x86 back end how generate 'lea' instructions, and generate by sewardj · 17 years ago
  32. 7fb65eb x86 back end: use 80-bit loads/stores for floating point spills rather by sewardj · 17 years ago
  33. 322bfa0 Support 'INT $3' instruction. by sewardj · 17 years ago
  34. e744153 Update copyright dates. by sewardj · 18 years ago
  35. a33e9a4 Update copyright dates. by sewardj · 18 years ago
  36. 5117ce1 Change the way Vex represents architecture variants into something by sewardj · 18 years ago
  37. ce02aa7 Merge in function wrapping support from the FNWRAP branch. That by sewardj · 19 years ago
  38. 0528bb5 Modify amd64 backend to use jump-jump scheme rather than call-return scheme. by sewardj · 19 years ago
  39. 17c7f95 - x86 back end: change code generation convention, so that instead of by sewardj · 19 years ago
  40. 92b6436 Added 'Bool mode64' to the various backend functions, to distinguish 32/64bit arch's. by cerion · 19 years ago
  41. a26f661 The earth's core is a vast mass of molten sse and sse2 instructions. by sewardj · 19 years ago
  42. 4fa325a API change: make the handling of syscall-denoting instructions a bit by sewardj · 19 years ago
  43. fb470fa Enable Xin_MFence on VexSubArchX86_sse0. by sewardj · 19 years ago
  44. c7cd214 Typechecker cleanups (non-functional changes) by sewardj · 19 years ago
  45. c4904af Don't emit cmovl since older x86s don't support it; instead emit a by sewardj · 19 years ago
  46. f07ed03 A minimal implementation of the x86 sysenter instruction by sewardj · 19 years ago
  47. 7bd6ffe by sewardj · 19 years ago
  48. dbcfae7 by sewardj · 19 years ago
  49. db4738a Basic support for self-checking translations. It fits quite neatly by sewardj · 19 years ago
  50. 8ee8c88 Another round of placating icc's typechecker. by sewardj · 19 years ago
  51. eba63f8 Cleaning up the x86 back end: get rid of instruction variants which by sewardj · 19 years ago
  52. cdcf00b Fix wrong comment. by sewardj · 19 years ago
  53. df53045 It seems we never generate x86 rotate insns, so get rid of these. by sewardj · 19 years ago
  54. 5dd5eb9 Fix misc naming things (unimportant) by sewardj · 19 years ago
  55. d3f9de7 Instruction selection/emission for Add64 and Sub64. by sewardj · 20 years ago
  56. bb3f52d Fix some minor things to do with memory fences and the Elan3 drivers. by sewardj · 20 years ago
  57. aade6d4 SSE2 fixes for mfence-ing. by sewardj · 20 years ago
  58. 3e83893 Add a trivial new IR construction: a memory fence statement. Connect by sewardj · 20 years ago
  59. 9ee8286 * x86 host: make SSE spills/restores work by sewardj · 20 years ago
  60. 52444cb Mechanism for dealing with failures of instruction decodes, and also by sewardj · 20 years ago
  61. 109ffdb x86 host: Stuff in support of memchecking of 64x2 vector FP. by sewardj · 20 years ago
  62. 70f676d More support for memchecking 128-bit SIMD code. by sewardj · 20 years ago
  63. 9e20359 Finish almost all SSE2 integer instructions. (!) by sewardj · 20 years ago
  64. b9fa69b x86 host/guest: SSE2 integer shifts and subtracts by sewardj · 20 years ago
  65. e5854d6 x86 guest/host: implement a whole bunch of SSE2 integer insns by sewardj · 20 years ago
  66. 164f927 IR level for support of 128 integer SIMD operations. Use this to do by sewardj · 20 years ago
  67. 636ad76 Copy-n-paste 32x4 floating point stuff into 64x2 floating point stuff so by sewardj · 20 years ago
  68. c1e7dfc Finish SSE1 instructions! Finallyatlast. by sewardj · 20 years ago
  69. 129b3d9 Fix a load of confusion with SSE scalar float insns and memory. by sewardj · 20 years ago
  70. 0bd7ce6 Even more SSE insns. by sewardj · 20 years ago
  71. 3bca906 Rationalisation/cleanup of float to/from int conversions and rounding by sewardj · 20 years ago
  72. 9636b44 x86 guest/host: a whole bunch more SSE instructions. by sewardj · 20 years ago
  73. 176a59c Add a bunch of easy SSE insns. by sewardj · 20 years ago
  74. 1e6ad74 x86 guest/host: do SSE comparisons. by sewardj · 20 years ago
  75. d08f2d7 x86 host: make a start on SSE code generation. by sewardj · 20 years ago
  76. 4a31b26 In the back end, rename the register classes (in enum HRegClass) more by sewardj · 20 years ago
  77. 893aada Create a new mechanism: "emulation warnings", which is a way for Vex by sewardj · 20 years ago
  78. c4278f4 Make VEX define the special thread-return-code values it uses. by sewardj · 20 years ago
  79. 43126d4 Handle Ijk_Yield properly. This fixes V regtest "none/tests/yield". by sewardj · 20 years ago
  80. 810dcf0 Make VEX's "Char" type always be signed, so as to bring it into line by sewardj · 20 years ago
  81. f8ed9d8 Add copyright notices. by sewardj · 20 years ago
  82. 8d38778 Fix some missing cases in printing FP insns. by sewardj · 20 years ago
  83. 358b7d4 Learn how to assemble an x86 negl insn. by sewardj · 20 years ago
  84. 218e29f x86 code generation for 64-bit integer stuff, required by Memchecking by sewardj · 20 years ago
  85. 45c50eb x86 back end: clear up confusion over which registers carry which by sewardj · 20 years ago
  86. 4b861de Make the x86 back end capable of generating conditional calls. by sewardj · 20 years ago
  87. 7735254 Implement regparm (1 to 3) in the x86 back end. by sewardj · 20 years ago
  88. 81ec418 New regime for baseblock layout, as described in comment in by sewardj · 20 years ago
  89. 12b0b88 Oops! Further update spill slot offsets following add of by sewardj · 20 years ago
  90. ee6eeca Temporary kludge to locate spill slots on cvs head. TODO: better by sewardj · 20 years ago
  91. 442d0be Implement IEEE754-compliant fprem1. by sewardj · 20 years ago
  92. b3944c2 Fix minor problems in x86 FP guest assembler. by sewardj · 20 years ago
  93. 99016a7 Implement guest x86 fptan. by sewardj · 20 years ago
  94. bec1084 x86 assembler: handle x86 FP reg-reg moves by sewardj · 20 years ago
  95. d7bd8ac More followups to previous increase of x86 FP regs from 4 to 6. by sewardj · 20 years ago
  96. eafde5a x86: Increase the number of available floating point registers in the by sewardj · 20 years ago
  97. 3f57c2d x86 host: do spill/reload of floating point registers. by sewardj · 20 years ago
  98. 06c32a0 Implement yet more x86 FP transcendental instructions. by sewardj · 20 years ago
  99. 8308aad Yet more x86 FP cases. by sewardj · 20 years ago
  100. 46de407 x86: implement FPREM (sigh, nasty, complicated) by sewardj · 20 years ago