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gerrit-public.fairphone.software / platform / external / valgrind / b3940763c0b8b934b9d16ab38f47a3749e3e078f
  1. b394076 Fix the guest state definition for s390x and introduce dummy members by florian · 13 years ago
  2. ad2c9ea VEX side fixes to match r12190, which is a fix for #279698 (incorrect by sewardj · 13 years ago
  3. ed0b953 Fix timerfd-syscall testcase on s390x. by florian · 13 years ago
  4. 260abb1 Handle Thumb2 ROR (register) encoding T2. #284472. by sewardj · 13 years ago
  5. 666e64c Ignore redundant REX.W on PTEST. #279071. (Jakub Jelinek, jakub@redhat.com) by sewardj · 13 years ago
  6. 94fb5b0 Handle PCMPxSTRx case 0x38. Fixes #273318. by sewardj · 13 years ago
  7. d881562 Implement the SSE4.1 insn PCMPEQQ. n-i-bz. (VEX side changes) by sewardj · 13 years ago
  8. bb75ba8 Implement SSE4.1 PMULUDQ. Fixes #280290. ** MERGE TO AVX ** by sewardj · 13 years ago
  9. f580065 Mark IR level calls and returns derived from ARM and Thumb code by sewardj · 13 years ago
  10. 4f9581e Ignore the precision flag in the ROUND{SS,SD,PS,PD} rounding mode. by tom · 13 years ago
  11. 6828dc7 arm backend: general (fallback) case handling for 64HLtoV128 by sewardj · 13 years ago
  12. 6d615ba Support ARM and Thumb "CLREX" instructions since Dalvik generates by sewardj · 13 years ago
  13. 1b2768a Add another slot on the stack frame used in the dispatcher. by florian · 13 years ago
  14. 2eeeb9b Document and assert that needs_self_check of VexTranslateArgs must not be NULL. by florian · 13 years ago
  15. 540acf5 Add a couple of spec rules for MI and PL after LOGIC. These are by sewardj · 13 years ago
  16. 26bc482 Add some counter arrays for profiling N,Z,C,V flag evaluations. by sewardj · 13 years ago
  17. 285c24d Add a couple more spec rules: LO after SUB and GT after SUB. by sewardj · 13 years ago
  18. 7b2f8f0 Enable move coalescing for Neon (vector) moves. Reduces code by sewardj · 13 years ago
  19. 262f5b9 Fix an obscure type error in printing of Neon instructions, that by sewardj · 13 years ago
  20. 6ad4952 Use mkite throughout. by florian · 13 years ago
  21. b0c9a13 Support CLCL and MVCL instructions. Based on a patch from by florian · 13 years ago
  22. e71e56a Add support for IBM Power ISA 2.06 -- stage 3. by sewardj · 13 years ago
  23. 87b48b6 Add support for s390x model z114. by florian · 13 years ago
  24. 3f5c03b Support "ENTER $imm16, $0"; some part of the OSX 10.7 library stack by sewardj · 13 years ago
  25. d6b43fd Support alternate (C0 /6) encoding of SHL on x86 and amd64. Fixes #209995. by tom · 13 years ago
  26. 81c22f0 Fix panic message. by florian · 13 years ago
  27. 5cdf4e3 Support an address size override prefix for REP prefixed string by tom · 13 years ago
  28. a4384a3 Add support for CKSM. by florian · 13 years ago
  29. e3aa016 Support FEMMS in x86 mode as we already do for amd64. Fix for #204574. by tom · 13 years ago
  30. 0fb4cbd Support XCHG AX, reg16 on amd64. Fixes #252695. by tom · 13 years ago
  31. 63d834e Supplement to r2189. Provide dummy function definition for non-s390 hosts. by florian · 13 years ago
  32. 30e8901 Handle the invalid opcode 0000. by florian · 13 years ago
  33. 7a08c10 Remove a redundant check. Found by Coverity. by florian · 13 years ago
  34. 2c8ed94 For a special opcode the address of the next insn was by florian · 13 years ago
  35. b0c1ed8 Fix an assert. by florian · 13 years ago
  36. 5fcbba2 Do not access addresses that belong to the client executable. by florian · 13 years ago
  37. 4aa412a Add support for IBM Power ISA 2.06 -- stage 2. Bug 276784. by sewardj · 13 years ago
  38. 51d26fd Comparing a boolean value for != 0 yields a result that is identical by florian · 13 years ago
  39. 420c501 Remove a redundant assert. Minor code tweaks. by florian · 13 years ago
  40. 2895832 Neon loads/stores: rename some vars, plus the main function, and add by sewardj · 13 years ago
  41. ea7eab7 Add algebraic simplification as follows: by florian · 13 years ago
  42. 7f5a841 Add support for Thumb2 encodings of PLD and PLDW. Bug 277653. by sewardj · 13 years ago
  43. f755839 Make VMOV.F32 load the correct value into the destination register. by sewardj · 13 years ago
  44. b706a0f Fix BLX r14 in ARM mode, which was broken due to incorrect sequencing by sewardj · 13 years ago
  45. a561f89 Fix NEON VMUL by float scalar. Bug 277663. (Mans Rullgard, mans@mansr.com) by sewardj · 13 years ago
  46. a99f20e Update a FIXME. Should have been included in r2174 by florian · 13 years ago
  47. a64c243 VEX-side changes to enable chasing of unconditional jumps/calls by florian · 13 years ago
  48. 3b49554 Tighten up an instruction decoding exception for add.w reg, sp, #constT. by sewardj · 13 years ago
  49. ff7f5b7 Complete the implementation of ARM atomic ops: {LD,ST}REX{,B,H,D} in by sewardj · 13 years ago
  50. 933065d Support the STFLE instruction via a dirty helper. by florian · 13 years ago
  51. dbf3d59 Add support for Thumb ADDW reg, reg, #uimm12 and SUBW ditto. Bug by sewardj · 13 years ago
  52. 0cd7473 Add a spec rule for NZ after LOGICQ, whilst chasing after a strange by sewardj · 13 years ago
  53. e88b3c9 Rename S390_GUEST_OFFSET to S390X_GUEST_OFFSET and use it throughout. by florian · 13 years ago
  54. b4df768 Misc s390x cleanups by florian · 13 years ago
  55. 66c8c9b Thumb2 front end: improved analysis of IT instructions that might by sewardj · 13 years ago
  56. 35da861 Get rid of redundant address mode calculation. by florian · 13 years ago
  57. c8c98fa Update ignored files for VEX. by florian · 13 years ago
  58. 5f438dd Rename and rationalise the vector narrowing and widening primops, so by sewardj · 13 years ago
  59. 9ee696a Reduce warning noise (make it in line with main Valgrind build) by sewardj · 13 years ago
  60. 718305c Unbreak Altivec support following r2159 (rename of saturating narrowing primops) by sewardj · 13 years ago
  61. 2260b99 Implement PACKUSDW (SSE4.1). Fixes #274776. by sewardj · 13 years ago
  62. c9bff7d Partially fix underspecification of saturating narrowing primops that by sewardj · 13 years ago
  63. bc161a4 Change the interface to LibVEX_Translate slightly, so as to make the by sewardj · 13 years ago
  64. e430418 Add some more spec rules, for performance purposes: by sewardj · 13 years ago
  65. 9cc2bbf Improvements to code generation for 32 bit instructions. When by sewardj · 13 years ago
  66. 010ac54 x86 and amd64 back ends: when generating transfers back to the by sewardj · 13 years ago
  67. 1ceb75b Comment-only change. by sewardj · 13 years ago
  68. 2f10aa6 Add a field 'UChar delta' to IRStmt_IMark, and use it to carry around by sewardj · 13 years ago
  69. 1e5fea6 s390x: provide clock instructions like STCK by sewardj · 13 years ago
  70. 3176386 ARM front end only: when processing Thumb instructions, create by sewardj · 13 years ago
  71. 7ee9752 Add LIKELY/UNLIKELY macros for general use, replacing s390x-specific by sewardj · 13 years ago
  72. cd2b025 s390x: fix DISP20 macro. Remove duplicate defn and avoid problems of by sewardj · 13 years ago
  73. 7d810d7 Handle Iop_I64UtoF32 in the ppc32/ppc64 insn selector. Fixes #270851. by sewardj · 13 years ago
  74. b3a860f Fix jump kind for indirect BLX for Thumb insns. Bug 266035 comment by sewardj · 13 years ago
  75. 5bb6ca2 Support DMB and DSB variants on Thumb. Bug 266035 comment 6. by sewardj · 13 years ago
  76. 54d75f7 Fix an assertion failure caused by r2144 (improved assertions to do by sewardj · 13 years ago
  77. 7e30807 Tighten up condition code handling in the back end, so as to placate by sewardj · 13 years ago
  78. e407ced Support DMB and DSB variants on ARM. Bug 266035 comment 3. by sewardj · 13 years ago
  79. f6d2cf9 Fix a bogus assertion observed by Florian Krohm. by sewardj · 13 years ago
  80. 13f12a5 Fix a nonsensical assertion observed by Florian Krohm. by sewardj · 13 years ago
  81. 99ff620 Add a spec rule for V after SUB. by sewardj · 13 years ago
  82. 3c14925 Split up armg_calculate_flags_nzcv into four functions that compute by sewardj · 13 years ago
  83. bb8b394 Improvements to condition code handling on ARM. by sewardj · 13 years ago
  84. d5436ce When simplifying (improving) the IR generated by the ARM front end, do by sewardj · 13 years ago
  85. d34e449 Handle Iop_Not64 when doing 32-bit code generation. Also, assert that by sewardj · 13 years ago
  86. 6900702 s390x : misc cleanups by sewardj · 13 years ago
  87. a52e37e s390x: Implement Ist_MBE by sewardj · 13 years ago
  88. a970c40 s390x: fix code confusion by sewardj · 13 years ago
  89. e0dd77e s390x: invalid use of R0 as base register by sewardj · 13 years ago
  90. d07b856 s390x: fpr - gpr transfer facility by sewardj · 13 years ago
  91. 95d6f3a Fix up incorrect usage of Iop_I64UtoF32 in the PowerPC front and back by sewardj · 13 years ago
  92. cb9ad0d Fix up some enum confusion to do with ARMNeonUnOp and ARMNeonUnOpS, as by sewardj · 13 years ago
  93. e522d4b Fix up enum confusion between PPCAvOp and PPCAvFpOp, as found by by sewardj · 13 years ago
  94. 66d5ef2 Add support for IBM Power ISA 2.06 -- stage 1. Bug #267630 and by sewardj · 13 years ago
  95. 652b56a s390x: reconsider "long displacement" requirement. We currently by sewardj · 13 years ago
  96. 15469da s390x: Make sure to point the PSW address to the next address on SIGILL by sewardj · 13 years ago
  97. b13a92a s390x: minor code generation tweaks. There were a few loose ends by sewardj · 13 years ago
  98. f74c86f s390x: tweak s390_emit_load_cc. #269864. (Florian Krohm, britzel@acm.org) by sewardj · 13 years ago
  99. 3c49aaa Remove unused parameter in functions s390_emit_SLL/SRL/SRA. by sewardj · 13 years ago
  100. d7bde72 Support conditional load and store for s390x (VEX side). by sewardj · 13 years ago