1. 363e606 Implement x86 insn popl m32. (Nikolay Igotti ) by sewardj · 22 years ago
  2. 95621db Yesterday's push/pop merging optimisations break the cache profiler: by sewardj · 22 years ago
  3. cfc39b2 Complain about NVidia's libGL.so also when an 0x8C opcode is encountered. by sewardj · 22 years ago
  4. e9c06f1 Implement SBB Ib, AL. by sewardj · 22 years ago
  5. 64a8cc4 Do LODSW / LODSL. (Sami Farin) by sewardj · 22 years ago
  6. a0f921a Only show the giant-basic-block message at verbosity >= 2. by sewardj · 22 years ago
  7. 4f51f9a Generate better ucode for back-to-back sequences of register pushes and by sewardj · 22 years ago
  8. 9316cba Improve accuracy of simulation of bsf/bsr instructions when the word by sewardj · 22 years ago
  9. 4f9c934 by njn · 22 years ago
  10. 5716dbb by sewardj · 22 years ago
  11. 969129d Add JCond-32 NP (long jump when parity odd) and CMOV NP too. by sewardj · 22 years ago
  12. 8d32be7 by sewardj · 22 years ago
  13. 79be106 Get rid of the muraroa.demon.co.uk references since that account is by sewardj · 22 years ago
  14. c7529c3 by sewardj · 22 years ago
  15. 0ece28b by sewardj · 22 years ago
  16. 22bafd9 by sewardj · 22 years ago
  17. 7f2a8bf by sewardj · 22 years ago
  18. 2e93c50 by sewardj · 22 years ago
  19. 4a7456e Detect FPU instructions which set %EFLAGS and mark the resulting by sewardj · 22 years ago
  20. fe8a166 Implement DAA as well as DAS. Byrial Jensen <byrial@image.dk> by sewardj · 22 years ago
  21. 3a72df0 (merge from 20020320) by sewardj · 22 years ago
  22. 4d0ab1f (merge from 20020320) Implement x86 das instruction. by sewardj · 22 years ago
  23. de4a1d0 Initial revision by sewardj · 22 years ago