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gerrit-public.fairphone.software / platform / external / valgrind / db01409d76d35700967e397745168a025020a9d0 / priv / host_x86_isel.c
  1. 96c5f26 Deal with CLFLUSH, which were not correctly dealt with (w.r.t. new IR by sewardj · 12 years ago
  2. c6f970f Add translation chaining support for amd64, x86 and ARM (VEX side). See #296422. by sewardj · 13 years ago
  3. e6c53e0 Update all copyright dates, from 20xy-2010 to 20xy-2011. by sewardj · 13 years ago
  4. ad2c9ea VEX side fixes to match r12190, which is a fix for #279698 (incorrect by sewardj · 13 years ago
  5. 5f438dd Rename and rationalise the vector narrowing and widening primops, so by sewardj · 13 years ago
  6. c9bff7d Partially fix underspecification of saturating narrowing primops that by sewardj · 13 years ago
  7. 50d89bf Save an instruction on the normal idiom generated for smc-checks. by sewardj · 14 years ago
  8. cc85558 Handle 16Uto64, which can now show up at the back end as a by sewardj · 14 years ago
  9. 536fbab Only decode LZCNT if the host supports it, since otherwise we risk by sewardj · 14 years ago
  10. b727161 Support the SSE4 insn 'roundss' in 32-bit mode. Lack of this was by sewardj · 14 years ago
  11. 752f906 Update copyright dates to 2010 and change license to standard GPL2+. by sewardj · 14 years ago
  12. 6c299f3 Merge r1925:1948 from branches/ARM. This temporarily breaks all other by sewardj · 15 years ago
  13. e768e92 by sewardj · 15 years ago
  14. 1fb8c92 Add new integer comparison primitives Iop_CasCmp{EQ,NE}{8,16,32,64}, by sewardj · 15 years ago
  15. cef7d3e by sewardj · 15 years ago[Renamed (99%) from priv/host-x86/isel.c]
  16. e9d8a26 Merge in branches/DCAS: by sewardj · 15 years ago
  17. 80d6e6d Fix a couple of longstanding enum inconsistencies discovered by by sewardj · 16 years ago
  18. 478646f Merge branches/OTRACK_BY_INSTRUMENTATION into the trunk. This by sewardj · 16 years ago
  19. a26d820 Update copyright dates ("200X-2007" --> "200X-2008"). by sewardj · 17 years ago
  20. 150c9cd by sewardj · 17 years ago
  21. 3252c07 Handle the case Add64(expr,const) a bit better. Apparently Massif The by sewardj · 17 years ago
  22. bf0d86c Fix stupid bug in x86 isel: when generating code for a 64-bit integer by sewardj · 17 years ago
  23. c4356f0 by sewardj · 17 years ago
  24. eb17e49 Merge from CGTUNE branch: by sewardj · 17 years ago
  25. fb7373a Merge, from CGTUNE branch: by sewardj · 17 years ago
  26. 79e04f8 Teach the x86 back end how generate 'lea' instructions, and generate by sewardj · 18 years ago
  27. fc1b541 Add 'missing' primop Iop_ReinterpF32asI32 and code generation support by sewardj · 18 years ago
  28. e744153 Update copyright dates. by sewardj · 18 years ago
  29. d71ba83 x86 front end: Implement MASKMOVQ (MMX class insn, introduced in SSE1) by sewardj · 18 years ago
  30. dd40fdf by sewardj · 18 years ago
  31. aca070a Merge r1663-r1666: by sewardj · 18 years ago
  32. a33e9a4 Update copyright dates. by sewardj · 18 years ago
  33. 8f07359 Counterpart to r1605: in the ppc insn selector, don't use the bits by sewardj · 18 years ago
  34. f47286e More x86 tidying up following rounding changes. by sewardj · 19 years ago
  35. f1b5b1a Followup to r1562: fixes for x86 by sewardj · 19 years ago
  36. b183b85 by sewardj · 19 years ago
  37. 5117ce1 Change the way Vex represents architecture variants into something by sewardj · 19 years ago
  38. 92b6436 Added 'Bool mode64' to the various backend functions, to distinguish 32/64bit arch's. by cerion · 19 years ago
  39. a26f661 The earth's core is a vast mass of molten sse and sse2 instructions. by sewardj · 19 years ago
  40. 300bb87 Implement cmpxchg8b. Sheesh. What a total dog of an instruction. by sewardj · 19 years ago
  41. 7bd6ffe by sewardj · 19 years ago
  42. dbcfae7 by sewardj · 19 years ago
  43. d45b446 Handle 0 :: Ity_I1 as well as 1 :: Ity_I1. by sewardj · 19 years ago
  44. af1ceca Enhance IR so as to distinguish between little- and big-endian loads and by sewardj · 19 years ago
  45. 27e1dd6 (API-visible change): generalise the VexSubArch idea. Everywhere by sewardj · 19 years ago
  46. 7f64c4c Handle NegF64. by sewardj · 19 years ago
  47. e5f740c These cases are now verified. by sewardj · 19 years ago
  48. e12d644 Support GetI/PutI of 32-bit integer arrays. by sewardj · 19 years ago
  49. 4a64fee Generate better code for CmpNEZ64(Or64(x,y)), a common idiom resulting by sewardj · 19 years ago
  50. 8ac39e4 Minor tweakage: use testl rather than andl in three places on the by sewardj · 19 years ago
  51. e5e8b56 Get rid of some functions made redundant by recent isel reorganisation. by sewardj · 19 years ago
  52. 0f1a488 by sewardj · 19 years ago
  53. 79d8a4b Comment-only change. by sewardj · 19 years ago
  54. 85619c4 iselIntExpr64(const): save a precious register in the case where by sewardj · 20 years ago
  55. 61825e0 Add a pattern for 64UtoV128(LDle:I64(addr)), so as to generate a by sewardj · 20 years ago
  56. 428fabd Make several more files compile cleanly with icc -Wall. Hopefully by sewardj · 20 years ago
  57. d2445f6 Add a new IR statement kind: IRStmt_NoOp, to denote a no-operation. by sewardj · 20 years ago
  58. f168931 by sewardj · 20 years ago
  59. 9a036bf Build fixes for gcc-2.96 (be more ANSI C compliant wrt placement by sewardj · 20 years ago
  60. eba63f8 Cleaning up the x86 back end: get rid of instruction variants which by sewardj · 20 years ago
  61. 3f5d7fa Add to-do note (comment-only change) by sewardj · 20 years ago
  62. f0c1c58 Consistently rename all existing IROps which operate on 128-bit values by sewardj · 20 years ago
  63. c2bcb6f Get a clean(er) build on amd64. Also a couple of amd64 fe/be fixes. by sewardj · 20 years ago
  64. f73b94a Fix bogus assertion. (How long has that been there?) by sewardj · 20 years ago
  65. 7883018 Record some shortcomings (comment-only change). by sewardj · 20 years ago
  66. d3f9de7 Instruction selection/emission for Add64 and Sub64. by sewardj · 20 years ago
  67. 1806918 Add new IR primops: Iop_CmpNEZ8x8, Iop_CmpNEZ16x4, Iop_CmpNEZ32x2 and by sewardj · 20 years ago
  68. 38a3f86 On x86 host and guest, re-implement the way MMX instructions are done, by sewardj · 20 years ago
  69. 9c32376 x86 floating point accuracy improvements. The aim is to make x86 FP by sewardj · 20 years ago
  70. 3e83893 Add a trivial new IR construction: a memory fence statement. Connect by sewardj · 20 years ago
  71. 9df271d Push subarchitecture stuff through the x86 parts. by sewardj · 20 years ago
  72. 41c3d4a iselCondCode: better handling of a pattern frequently generated by memcheck. by sewardj · 20 years ago
  73. 69933ac Move the IR tree matcher into its own module to get rid of duplication. by sewardj · 20 years ago
  74. 4ea793f Special case for CmpNE64(x,0), which is frequently generated when by sewardj · 20 years ago
  75. 2e38386 x86 guest/host: fix enough 128-bit vector stuff that memcheck works for by sewardj · 20 years ago
  76. 109ffdb x86 host: Stuff in support of memchecking of 64x2 vector FP. by sewardj · 20 years ago
  77. a0037df Stuff needed for Memcheck of SSE1 instructions. by sewardj · 20 years ago
  78. 70f676d More support for memchecking 128-bit SIMD code. by sewardj · 20 years ago
  79. 9e20359 Finish almost all SSE2 integer instructions. (!) by sewardj · 20 years ago
  80. b9fa69b x86 host/guest: SSE2 integer shifts and subtracts by sewardj · 20 years ago
  81. e5854d6 x86 guest/host: implement a whole bunch of SSE2 integer insns by sewardj · 20 years ago
  82. 164f927 IR level for support of 128 integer SIMD operations. Use this to do by sewardj · 20 years ago
  83. 008754b x86 guest: finish SSE2 floating point insns. by sewardj · 20 years ago
  84. fd22645 x86 guest: Implement a whole bunch of SSE2 instructions, mostly by sewardj · 20 years ago
  85. 636ad76 Copy-n-paste 32x4 floating point stuff into 64x2 floating point stuff so by sewardj · 20 years ago
  86. 855f32d Make small procedures to add/sub small amounts from esp. by sewardj · 20 years ago
  87. c1e7dfc Finish SSE1 instructions! Finallyatlast. by sewardj · 20 years ago
  88. 129b3d9 Fix a load of confusion with SSE scalar float insns and memory. by sewardj · 20 years ago
  89. 0bd7ce6 Even more SSE insns. by sewardj · 20 years ago
  90. 3bca906 Rationalisation/cleanup of float to/from int conversions and rounding by sewardj · 20 years ago
  91. 9636b44 x86 guest/host: a whole bunch more SSE instructions. by sewardj · 20 years ago
  92. 176a59c Add a bunch of easy SSE insns. by sewardj · 20 years ago
  93. 4cb918d Mucho messing around with x86 FP/SSE rounding modes etc. As a result by sewardj · 20 years ago
  94. 67e002d x86 guest/host: do SSE comiss instruction by sewardj · 20 years ago
  95. 1e6ad74 x86 guest/host: do SSE comparisons. by sewardj · 20 years ago
  96. d08f2d7 x86 host: make a start on SSE code generation. by sewardj · 20 years ago
  97. 4a31b26 In the back end, rename the register classes (in enum HRegClass) more by sewardj · 20 years ago
  98. 893aada Create a new mechanism: "emulation warnings", which is a way for Vex by sewardj · 20 years ago
  99. f27e1db Do 32Uto64. by sewardj · 20 years ago
  100. 8fc9374 gcc-2.95 build fixes. by sewardj · 20 years ago