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gerrit-public.fairphone.software / platform / external / valgrind / e71e56a90e91ce37b0ee846a4ff94493d59f2095 / priv / host_ppc_defs.c
  1. e71e56a Add support for IBM Power ISA 2.06 -- stage 3. by sewardj · 13 years ago
  2. 4aa412a Add support for IBM Power ISA 2.06 -- stage 2. Bug 276784. by sewardj · 13 years ago
  3. 010ac54 x86 and amd64 back ends: when generating transfers back to the by sewardj · 13 years ago
  4. 7d810d7 Handle Iop_I64UtoF32 in the ppc32/ppc64 insn selector. Fixes #270851. by sewardj · 13 years ago
  5. 7e30807 Tighten up condition code handling in the back end, so as to placate by sewardj · 13 years ago
  6. e522d4b Fix up enum confusion between PPCAvOp and PPCAvFpOp, as found by by sewardj · 13 years ago
  7. 66d5ef2 Add support for IBM Power ISA 2.06 -- stage 1. Bug #267630 and by sewardj · 13 years ago
  8. 752f906 Update copyright dates to 2010 and change license to standard GPL2+. by sewardj · 14 years ago
  9. 2a0cc85 gen{Spill,Reload}_PPC: track recent change in genSpill/Reload signature. by sewardj · 15 years ago
  10. cef7d3e by sewardj · 15 years ago[Renamed (99%) from priv/host-ppc/hdefs.c]
  11. e9d8a26 Merge in branches/DCAS: by sewardj · 15 years ago
  12. 0f1ef86 Handle frin, frim, frip, friz, in 64-bit mode only, for now. by sewardj · 16 years ago
  13. a26d820 Update copyright dates ("200X-2007" --> "200X-2008"). by sewardj · 17 years ago
  14. 0f50004 Support x86 $int 0x40 .. 0x43 instructions on Linux. Apparently these by sewardj · 17 years ago
  15. eb17e49 Merge from CGTUNE branch: by sewardj · 17 years ago
  16. 34085e3 When generating 64-bit code, ensure that any addresses used in 4 or 8 by sewardj · 18 years ago
  17. e744153 Update copyright dates. by sewardj · 18 years ago
  18. aca070a Merge r1663-r1666: by sewardj · 18 years ago
  19. a33e9a4 Update copyright dates. by sewardj · 18 years ago
  20. afd1639 Fix for 32-bit mode, as per comment. by sewardj · 18 years ago
  21. 40c8026 Redo the way FP multiply-accumulate insns are done on ppc32/64. by sewardj · 19 years ago
  22. 334870d ppc32/64: handle twi/tdi (conditional trap) instructions by sewardj · 19 years ago
  23. b183b85 by sewardj · 19 years ago
  24. baf971a Handle ppc32/64 fres, frsqrte. by sewardj · 19 years ago
  25. 7fd5bb0 A bit more backend tidying: by sewardj · 19 years ago
  26. 92923de by sewardj · 19 years ago
  27. 9dd9cf1 Add Ijk_EmFail, a new kind of IR block exit: an emulation failure by sewardj · 19 years ago
  28. ce02aa7 Merge in function wrapping support from the FNWRAP branch. That by sewardj · 19 years ago
  29. cb1f68e Handle dcbz in 64-bit mode. by sewardj · 19 years ago
  30. 7594920 Comment only changes - misc refs to ppc32 changed to ppc. by cerion · 19 years ago
  31. d0eae2d renamed VEX dirs guest-ppc32/ -> guest-ppc/, host-ppc32/ -> host-ppc/ by cerion · 19 years ago[Renamed (99%) from priv/host-ppc32/hdefs.c]
  32. 5b2325f Changed naming convention from 'PPC32' to 'PPC' for all VEX code common to both PPC32 and PPC64. by cerion · 19 years ago
  33. 07b07a9 Implemented almost all of the remaining 64bit-mode insns. by cerion · 19 years ago
  34. bb01b7c Fixed up front and backend for 32bit mul,div,cmp,shift in mode64 by cerion · 19 years ago
  35. f774505 ppc32/64 backend: take r29 out of circulation so the Valgrind by sewardj · 19 years ago
  36. b8a8dba Make suitable changes for ppc32/ppc64 following recent x86/amd64 by sewardj · 19 years ago
  37. 18e3189 Stop gcc complaining. by sewardj · 19 years ago
  38. f0de28c Implemented backend for ppc64, sharing ppc32 backend. by cerion · 19 years ago
  39. 92b6436 Added 'Bool mode64' to the various backend functions, to distinguish 32/64bit arch's. by cerion · 19 years ago
  40. d963eb4 Implemented most of the remaining altivec fp ops: by cerion · 19 years ago
  41. f7da610 gcc4 picked up a typo. by cerion · 19 years ago
  42. 8ea0d3e Frontend by cerion · 19 years ago
  43. 4a49b03 Frontend: by cerion · 19 years ago
  44. 1ac656a New irop Iop_MullEven* - a widening un/signed multiply of even lanes by cerion · 19 years ago
  45. 4fa325a API change: make the handling of syscall-denoting instructions a bit by sewardj · 19 years ago
  46. 62d0543 Tidy up a couple of format strings. by sewardj · 19 years ago
  47. dc1f913 Fill in a few missing Altivec cases: by sewardj · 19 years ago
  48. 197bd17 Build fixes for gcc-2.96 (which does not allow declarations after the by sewardj · 19 years ago
  49. f34ccc4 spacing and var name chages only by cerion · 19 years ago
  50. 92d9d87 Added AltiVec permutation insns: - vperm, vsldoi, vmrg*, vsplt* by cerion · 19 years ago
  51. 36991ef Implemented simple AltiVec arithmetic insns: by cerion · 19 years ago
  52. d3e5241 implemented vaddcuw by cerion · 19 years ago
  53. 27b3d7e more altivec insns: vsr, vspltw - only working with with --tool=none by cerion · 19 years ago
  54. 225a034 by cerion · 19 years ago
  55. c7cd214 Typechecker cleanups (non-functional changes) by sewardj · 19 years ago
  56. 6a64a9f On a PPC32Instr_Call, don't merely record how many integer registers by sewardj · 19 years ago
  57. 7bd6ffe by sewardj · 19 years ago
  58. dbcfae7 by sewardj · 19 years ago
  59. b51f0f4 by sewardj · 19 years ago
  60. 7d7f1b6 A further hack to reduce ppc32 reg-alloc costs: don't give the by sewardj · 19 years ago
  61. db36c0f Type casting cleanups. by sewardj · 19 years ago
  62. a5f957d Fix backend bug: the immediate on PPC32AMode_IR is 16 bits signed, not unsigned. by sewardj · 19 years ago
  63. 0171310 We have more than 59 allocateable regs now (duh) by cerion · 19 years ago
  64. 91c62fd Fixed coupla altivec typos - hopefully fixes FC4 build by cerion · 19 years ago
  65. 6b6f59e Reshuffled host-ppc32 AltiVec integer insns Added some AltiVec fp insns and CMov by cerion · 19 years ago
  66. c3d8bdc PPC32 AltiVec host-end framework & intruction output - no fp yet by cerion · 19 years ago
  67. 9762bbf Fix ppc32 'Call' bug by cerion · 19 years ago
  68. 094d139 Floating-point for ppc32 by cerion · 19 years ago
  69. ed623db guest-ppc32 by cerion · 19 years ago
  70. 428fabd Make several more files compile cleanly with icc -Wall. Hopefully by sewardj · 20 years ago
  71. 7ce9d15 Support for vex-directed instruction-cache invalidation, needed for by sewardj · 20 years ago
  72. 99f3577 Fix backend cntlzw by cerion · 20 years ago
  73. a2f7588 Cleanup backend: var name chages like src1,2 -> srcL,R etc by cerion · 20 years ago
  74. 9a036bf Build fixes for gcc-2.96 (be more ANSI C compliant wrt placement by sewardj · 20 years ago
  75. 9e263e3 Cleaned up backend a little by cerion · 20 years ago
  76. 47c526b Cleaned up isel for instns taking an RI arg by cerion · 20 years ago
  77. b8c3b7f Small backend printout changes only by cerion · 20 years ago
  78. 35663a7 Backend bug: mkFormD wasn't smallifying the imm by cerion · 20 years ago
  79. 5e2527e Alu32::SUB was broken in the backend. by cerion · 20 years ago
  80. fbda9b7 Fixed a backend shift bug: src/dst were swapped in emitted code. by cerion · 20 years ago
  81. f9d6e22 Just some assembly printout changes by cerion · 20 years ago
  82. 7f000af Added new instruction RdWrLR to read/write link register. by cerion · 20 years ago
  83. 8c51ed4 Better assembly printouts, and added iselCondCode 1:Bit Const by cerion · 20 years ago
  84. 9a934a9 just turned off some debug printfs by cerion · 20 years ago
  85. e97e106 Fixes to host_ppc32: by cerion · 20 years ago
  86. a56e9cc Cleaned up a little more by cerion · 20 years ago
  87. 7cf8e4e Fixed emit_PPC32Instr::Pin_Goto by cerion · 20 years ago
  88. fd0b87f Emitted Div, fixed mul... that's the lot for return0.orig\! by cerion · 20 years ago
  89. 98411db hdefs by cerion · 20 years ago
  90. 33aa6da More instr emitting: - most 'forms' done - had a go at Pin_Call, Pin_Goto by cerion · 20 years ago
  91. b85e8bb spacing/comment cleanup only by cerion · 20 years ago
  92. ab9132d Sorted out the condcode stuff - hopefully correctly... by cerion · 20 years ago
  93. c056a88 and now emit instrs big-endianly... :-) by cerion · 20 years ago
  94. d5e3838 Added the first instrs (load,store) to emit_PPC32Instr() by cerion · 20 years ago
  95. c0e707e Added Div32 - that's the last for this .orig file! by cerion · 20 years ago
  96. e13bb31 Added CLZ Fixed Unary32 Added genSpill_PPC32, genReload_PPC32 by cerion · 20 years ago
  97. 92f5dc7 hdefs: MulL, MFence by cerion · 20 years ago
  98. b536af9 hdefs: CMov32, Set32 by cerion · 20 years ago
  99. 3c0b12b Dealt with some cases where imm > 0xFFFF by cerion · 20 years ago
  100. b4a632a Changed the register setup a little by cerion · 20 years ago