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gerrit-public.fairphone.software / platform / external / valgrind / ec0d9a028955060c5216341c6fc37400ec0cb4be
  1. ec0d9a0 Merge from branches/THUMB: hwcaps for ARM. May get simplified since by sewardj · 14 years ago
  2. 6c60b32 Merge from branches/THUMB: back end changes to support NEON code generation. by sewardj · 14 years ago
  3. d266447 Merge from branches/THUMB: front end changes to support: by sewardj · 14 years ago
  4. be91791 Merge from branches/THUMB: A spechelper interface change that allows by sewardj · 14 years ago
  5. b54152a Enable SSE 4.1 and 4.2 by default on x86_64. (x86 remains stuck by sewardj · 14 years ago
  6. acfbd7d Add a moderately comprehensive implementation of the SSE4.2 string by sewardj · 14 years ago
  7. 0b2d3fe Add partial support for the SSE 4.2 PCMPISTRI instruction, at least by sewardj · 14 years ago
  8. 3d73810 Update for Core iX. by sewardj · 14 years ago
  9. 0283430 Don't trash the ELF ABI redzone for amd64 when emulating BT{,S,R,C} by sewardj · 14 years ago
  10. 287e9bb Add a folding rule for 32Sto64. by sewardj · 14 years ago
  11. 536fbab Only decode LZCNT if the host supports it, since otherwise we risk by sewardj · 14 years ago
  12. 9a660ea Support the amd SSE4.something LZCNT instruction. Fixes #212335 by sewardj · 14 years ago
  13. 57b0ba5 Handle mov[ua[pd G(xmm) -> E(xmm) case, which is something binutils by sewardj · 14 years ago
  14. 772f6df x86/amd64 FXTRACT: mimic the Core i5 behaviour when the argument is a by sewardj · 14 years ago
  15. 0fb6994 Ignore a redundant REX.W prefix on an MMX pinsrw instruction by sewardj · 14 years ago
  16. 95aa910 Add a program for printing out cpuid info. by sewardj · 14 years ago
  17. b727161 Support the SSE4 insn 'roundss' in 32-bit mode. Lack of this was by sewardj · 14 years ago
  18. d15b597 Implement ROUNDSS (partial implementation, in the case where by sewardj · 14 years ago
  19. 39aefda Implement ROUNDSD (partial implementation, in the case where by sewardj · 14 years ago
  20. 69d98e3 Implement SSE4 instructions: PCMPGTQ PMAXUD PMINUD PMAXSB PMINSB PMULLD by sewardj · 14 years ago
  21. fd18128 Implement more SSE4 instructions: PINSRD PMINUD POPCNTW POPCNTL POPCNTQ by sewardj · 14 years ago
  22. b9dc243 Implement SIDT and SGDT as pass-throughs to the host. It's a pretty by sewardj · 14 years ago
  23. c2433a8 Implement XADD reg,reg (Nicolas Sauzede, nicolas.sauzede@st.com). Fixes #195662. by sewardj · 14 years ago
  24. 9f5c8fd Enable FISTS. Fixes #234037. (Bradley Baetz, bbaetz@gmail.com) by sewardj · 14 years ago
  25. 412098c Handle v7 memory fence instructions: ISB DSB DMB and their v6 equivalents: by sewardj · 14 years ago
  26. deceef8 Handle more x86 NOP forms, as required by Fedora 13. Fixes bug by sewardj · 14 years ago
  27. 752f906 Update copyright dates to 2010 and change license to standard GPL2+. by sewardj · 14 years ago
  28. 2febc60 (re-commit r1976): Added new SSE4.1 instruction: PMAXUD by sewardj · 14 years ago
  29. e53a5e0 (re-commit r1975): Added new SSE4.1 instruction: PINSRQ by sewardj · 14 years ago
  30. 38523e9 (re-commit r1974): Fix up printing for some of the SSE4.1 insns. by sewardj · 14 years ago
  31. e76895d (re-commit r1973): by sewardj · 14 years ago
  32. 4342831 (re-commit r1972): Fixed copy+paste error in R1971 by sewardj · 14 years ago
  33. 733d589 (re-commit r1971) Added new SSE4 instructions PMINSD, PMAXSD. by sewardj · 14 years ago
  34. a1c1d9a (re-commit r1970): Tested BLENDPS Added new SSE4 instructions DPPD and DPPS by sewardj · 14 years ago
  35. d403e79 iselVecExpr_wrk: 128-bit constants: handle all 16 cases by de · 14 years ago
  36. b5afdbd Added new SSE4 instruction BLENDPS (backend needs a fix before testing) by de · 14 years ago
  37. 7cfc306 Enable PMOVSXBW and fix lane shift widths. by sewardj · 14 years ago
  38. 9ba870d Handle a few more cases in 128-bit constant generation, needed by by sewardj · 14 years ago
  39. 5a70f5c by de · 14 years ago
  40. 04ac5de Support FTOUIS, UXTAB, SXTAH. by sewardj · 14 years ago
  41. f7d3b2e Handle SBB Eb,Gb. by sewardj · 15 years ago
  42. 4df975f Fix incorrect spec rule for LE after INCB, for end-of range cases (arg = 0x7F). by sewardj · 15 years ago
  43. 30a20e9 CVTPI2PD (which converts 2 x I32 in M64 or MMX to 2 x F64 in XMM): by sewardj · 15 years ago
  44. 9581906 Majorly improved implementation of self-checking for translations. by sewardj · 15 years ago
  45. 0d925b1 x86/amd64 front ends: don't chase a conditional branch that leads by sewardj · 15 years ago
  46. 82f5688 Enable (optionally) chasing through conditional branches during trace by sewardj · 15 years ago
  47. 984d9b1 by sewardj · 15 years ago
  48. ff6b34a amd64: add a couple more spec cases: NLE after SUBL, and NZ after LOGICB. by sewardj · 15 years ago
  49. ef425db For 32-bit reads of integer guest registers, generate a 64-bit Get by sewardj · 15 years ago
  50. 80bea7b * support PLD (cache-preload-hint) instructions by sewardj · 15 years ago
  51. abb429b Don't force alignment for LDMxx/STMxx when presented with a misaligned by sewardj · 15 years ago
  52. 2a0cc85 gen{Spill,Reload}_PPC: track recent change in genSpill/Reload signature. by sewardj · 15 years ago
  53. 445dbef Generate a couple more ARM specific offsets; also R1 on ppc32/64. by sewardj · 15 years ago
  54. 2a1ed8e Make the x86 and amd64 back ends use the revised prototypes for by sewardj · 15 years ago
  55. 6c299f3 Merge r1925:1948 from branches/ARM. This temporarily breaks all other by sewardj · 15 years ago
  56. 8688a72 Testing hacklet, to fill the vex tmp allocation area before each by sewardj · 15 years ago
  57. e768e92 by sewardj · 15 years ago
  58. 95e154c Use a shorter instruction encoding for "mov $smallish positive int, %reg". by sewardj · 15 years ago
  59. 3b09235 Specialise "S after 32-bit SUB/CMP"; improves performance by about 2% by sewardj · 15 years ago
  60. 32bf791 Track recent file renaming. by sewardj · 15 years ago
  61. 36af94c Update ("cand1" committed for real use in immediately preceding r1918). by sewardj · 15 years ago
  62. 5eaf82b Use a much faster hash function to do the self-modifying-code checks. by sewardj · 15 years ago
  63. 1485935 Add test program for experimentation with smc-check hashing schemes by sewardj · 15 years ago
  64. 01f8cce Print raw machine code in an easier-to-parse way. by sewardj · 15 years ago
  65. 37b2ee8 Implement mfpvr (mfspr 287) (bug #201585). by sewardj · 15 years ago
  66. 9e341ca Tell the register allocator on x86 that xmm0..7 are trashed across by sewardj · 15 years ago
  67. 0f99be6 Support LODS on amd64. Fixes #189737. by sewardj · 15 years ago
  68. 05a2c38 deepCopyIRCAS: handle NULL dataHi and expdHi without segfaulting. by sewardj · 15 years ago
  69. 3187dc7 Get rid of LibVEX_Version(). by sewardj · 15 years ago
  70. 40d1d21 Fix disassembly printing of cmpxchg insns (don't print "lock" twice). by sewardj · 15 years ago
  71. 1fb8c92 Add new integer comparison primitives Iop_CasCmp{EQ,NE}{8,16,32,64}, by sewardj · 15 years ago
  72. 9c2f13d Fix ppc64 guest layout description following recent DCAS hackery. by sewardj · 15 years ago
  73. ff99b07 Unbreak the svn-version thing following r1904. by sewardj · 15 years ago
  74. cef7d3e by sewardj · 15 years ago
  75. d652012 Double the size of the spill area. Fixes #195838. by sewardj · 15 years ago
  76. c984765 Rename 'Makefile' to 'Makefile-gcc' so as to be compatible with recent by sewardj · 15 years ago
  77. e9d8a26 Merge in branches/DCAS: by sewardj · 15 years ago
  78. 16a5960 Use more POSIX-standard flags for 'ar'. See #195287. by sewardj · 15 years ago
  79. 90472eb Make VexGuestAMD64State have a 16-aligned size once again, following r1886. by sewardj · 15 years ago
  80. f30883e Calculate next %rip correctly in palignr instructions (mmx and xmm-class). by sewardj · 15 years ago
  81. e86310f In order to make it possible for Valgrind to restart client syscalls by sewardj · 15 years ago
  82. 4771230 Change underscores in the middle of library names into dashes. by sewardj · 16 years ago
  83. 2306332 Handle redundant REX.W on PUNPCKHgg. Fixes test case dated 2009-01-22 by sewardj · 16 years ago
  84. ceccb29 Handle both %gs and %fs prefixes on amd64 a bit more "properly". by sewardj · 16 years ago
  85. d2dc14a genoffsets.c: don't use __builtin_offset since older gcc's don't by sewardj · 16 years ago
  86. ba69ffb Change the way pub/libvex_guest_offsets.h is created, so that it is by sewardj · 16 years ago
  87. 7bdd1bc Handle some redundant REX.W prefixes on code from IPP (Intel by sewardj · 16 years ago
  88. 2e28ac4 by sewardj · 16 years ago
  89. d660d41 Initial VEX-end support for Darwin (x86 and amd64). by sewardj · 16 years ago
  90. b7ba04f Handle "movsd G,E" for G and E both regs. This is the non-binutils by sewardj · 16 years ago
  91. 7d8f137 Support "repe scas" on amd64. Fixes #168943. by sewardj · 16 years ago
  92. 1685c28 Tighten up decoding of isel instruction. by sewardj · 16 years ago
  93. cb07be2 Support isel (integer conditional move). by sewardj · 16 years ago
  94. e5e837c Handle MOVSD reg,reg for the encoding which is not emitted by binutils. by sewardj · 16 years ago
  95. ecbaee7 Fixes for compilation warnings from the apparently very strict by sewardj · 16 years ago
  96. 792d771 In 32-bit mode only, accept primary opcode 0x82 and treat it the same by sewardj · 16 years ago
  97. 72cd337 Stop gcc-4.4.0 (snapshot) complaining about strict-aliasing violations. by sewardj · 16 years ago
  98. 4970e4e Support FPREM1 on amd64. Fixes #172563. by sewardj · 16 years ago
  99. a203330 Add a description of the FP offset/size to type VexGuestLayout. by sewardj · 16 years ago
  100. 2b8db3e C89 fixes (stop gcc complaining). by sewardj · 16 years ago