Allow CougarPoint as a valid GPIO controller.
BUG=chrome-os-partner:4879
TEST=manual (just try it)
NOTE: You must use a BIOS that exports the correct ACPI tables.
Change-Id: I027680a203f3a566edf9ed82fb1fe1a9fa4c4f0f
Reviewed-on: http://gerrit.chromium.org/gerrit/4957
Tested-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
diff --git a/host/arch/x86/lib/crossystem_arch.c b/host/arch/x86/lib/crossystem_arch.c
index 670ce36..1db81fd 100644
--- a/host/arch/x86/lib/crossystem_arch.c
+++ b/host/arch/x86/lib/crossystem_arch.c
@@ -452,17 +452,19 @@
if (active_high == -1 || controller_offset == -1)
return -1; /* Missing needed info */
- /* We only support the NM10 for now */
+ /* Check for chipsets we recognize. */
snprintf(name, sizeof(name), "%s.%d/GPIO.3", ACPI_GPIO_PATH, index);
if (!ReadFileString(controller_name, sizeof(controller_name), name))
return -1;
- if (0 != strcmp(controller_name, "NM10"))
+ if ((0 != strcmp(controller_name, "NM10")) &&
+ (0 != strcmp(controller_name, "CougarPoint")))
return -1;
- /* Assume the NM10 has offset 192 */
- /* TODO: should really check gpiochipNNN/label to see if it's the
- * address we expect for the NM10, and then read the offset from
- * gpiochipNNN/base. */
+ /* We blindly assume the controller has offset 192.
+ * There is some information under /sys/class/gpio/gpiochip192/,
+ * but there's nothing there to correlate that with anything we already
+ * discovered, so if it's not the right thing we have no way of knowing.
+ */
controller_offset += 192;
/* Try reading the GPIO value */