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gerrit-public.fairphone.software / platform / external / vixl / 83a4d4fff37ace509c4c19f16addbbd565cfcde3
commit83a4d4fff37ace509c4c19f16addbbd565cfcde3[log] [tgz]
authorScott Wakeling <scott.wakeling@linaro.org>Thu Dec 22 14:21:27 2016 +0000
committerScott Wakeling <scott.wakeling@linaro.org>Thu Dec 22 14:25:04 2016 +0000
treeaae88334522073789344b179e9985ed9a6f6207e
parent467c20c0dcdcbfa508d4cbc7dcc6b4d5fe073056 [diff]
parent5767b11e43b09788de8a899aafa1a307f1fef2a1 [diff]
Merge remote-tracking branch 'aosp/upstream-master' into master

5767b11 Specify CodeBuffer allocator type for ARM and ARM64.
d836966 [aarch32] Dot not abort when one uses unpredictable or strongly discouraged instructions
942e3b7 Add unpredictable conditions for mov.
a576eb9 Add more identities.
34ecc5b Move some NO_RETURN attributes.
dd63b6b Do not call AArch64's EnsureIAndDCacheCoherency if the target is AArch32 only
745a855 Add a missing no-return attribute.
14e3bf1 Test code size after commutation.
028fb05 Improve and clean up abort messages.
1fa6f06 Allow configuration of the CodeBuffer allocator.
e8ce9f0 Assert perfect nesting for UseScratchRegisterScope.
1091d74 Generate ADD and not ADDS for Add(DontCare, r1, r1, r2).
5ddbc80 Optimize IsModifiedImmediate and Orn/Orns delegate.
2f885bb Add option to skip generation of dummy traces in tools/generate_tests.py.
be9c4d0 Support conditional load literal for T32.
287e6d1 Convert markdown to html with `scons doc`
1c1488c Make test.py build with different values for target_arch
8253a3c Introduce option validator in SCons
196ab77 [aarch32] Fix test-operands build with target_arch=aarch64
cf91ee6 Make rewinding of load literal instructions less conservative.
b2f05e6 [aarch32] Remove deprecated tests of PC as destination of MOV{s} and MVN{S}
50e45c5 After rewinding a load, only add the label to the literal pool if it's not bound.
5754469 [aarch32] Cleanup *_pool_in_delegate tests
4f002a8 Increase max recursion limit for delegates.
efe0c1f Allow Operand::From to convert signed integrals
1edc01c A dedicated test file for UseScratchRegisterScope.
4a30c5d Add MacroAssembler B with hint.
67b839b Add a fuzzing test for Cbz, Bind etc.
e31fda5 Correct number of bytes we check we can emit in ITScope.
9ae5da2 Specify instructions which use a delegate.
18908fb aarch32: Add some basic test for blx.

Test: top-level `make -j40`
      `mma -j40 test-art-target-test-optimizing dist`
      `mma -j40 test-art-host dist`
Change-Id: I3d656224fd4151904b8096486adecb6ef1eafea6
tree: aae88334522073789344b179e9985ed9a6f6207e
  1. benchmarks/
  2. doc/
  3. examples/
  4. src/
  5. test/
  6. tools/
  7. .clang-format
  8. .gitignore
  9. .gitreview
  10. .ycm_extra_conf.py
  11. Android.bp
  12. Android.mk
  13. AUTHORS
  14. CPPLINT.cfg
  15. LICENCE
  16. README.md
  17. README.version
  18. SConstruct
README.md

VIXL: AArch64 Runtime Code Generation Library Version 1.13

Contents:

  • Overview
  • Licence
  • Requirements
  • Known limitations
  • Usage

Overview

VIXL contains three components.

  1. A programmatic assembler to generate A64 code at runtime. The assembler abstracts some of the constraints of the A64 ISA; for example, most instructions support any immediate.
  2. A disassembler that can print any instruction emitted by the assembler.
  3. A simulator that can simulate any instruction emitted by the assembler. The simulator allows generated code to be run on another architecture without the need for a full ISA model.

The VIXL git repository can be found on GitHub.

Changes from previous versions of VIXL can be found in the Changelog.

Licence

This software is covered by the licence described in the LICENCE file.

Requirements

To build VIXL the following software is required:

  1. Python 2.7
  2. SCons 2.0
  3. GCC 4.8+ or Clang 3.4+

A 64-bit host machine is required, implementing an LP64 data model. VIXL has been tested using GCC on AArch64 Debian, GCC and Clang on amd64 Ubuntu systems.

To run the linter and code formatting stages of the tests, the following software is also required:

  1. Git
  2. Google's cpplint.py
  3. clang-format-3.6

Refer to the 'Usage' section for details.

Known Limitations

VIXL was developed for JavaScript engines so a number of features from A64 were deemed unnecessary:

  • Limited rounding mode support for floating point.
  • Limited support for synchronisation instructions.
  • Limited support for system instructions.
  • A few miscellaneous integer and floating point instructions are missing.

The VIXL simulator supports only those instructions that the VIXL assembler can generate. The doc directory contains a list of supported instructions.

The VIXL simulator was developed to run on 64-bit amd64 platforms. Whilst it builds and mostly works for 32-bit x86 platforms, there are a number of floating-point operations which do not work correctly, and a number of tests fail as a result.

VIXL may not build using Clang 3.7, due to a compiler warning. A workaround is to disable conversion of warnings to errors, or to delete the offending return statement reported and rebuild. This problem will be fixed in the next release.

Debug Builds

Your project's build system must define VIXL_DEBUG (eg. -DVIXL_DEBUG) when using a VIXL library that has been built with debug enabled.

Some classes defined in VIXL header files contain fields that are only present in debug builds, so if VIXL_DEBUG is defined when the library is built, but not defined for the header files included in your project, you will see runtime failures.

Exclusive-Access Instructions

All exclusive-access instructions are supported, but the simulator cannot accurately simulate their behaviour as described in the ARMv8 Architecture Reference Manual.

  • A local monitor is simulated, so simulated exclusive loads and stores execute as expected in a single-threaded environment.
  • The global monitor is simulated by occasionally causing exclusive-access instructions to fail regardless of the local monitor state.
  • Load-acquire, store-release semantics are approximated by issuing a host memory barrier after loads or before stores. The built-in __sync_synchronize() is used for this purpose.

The simulator tries to be strict, and implements the following restrictions that the ARMv8 ARM allows:

  • A pair of load-/store-exclusive instructions will only succeed if they have the same address and access size.
  • Most of the time, cache-maintenance operations or explicit memory accesses will clear the exclusive monitor.
    • To ensure that simulated code does not depend on this behaviour, the exclusive monitor will sometimes be left intact after these instructions.

Instructions affected by these limitations: stxrb, stxrh, stxr, ldxrb, ldxrh, ldxr, stxp, ldxp, stlxrb, stlxrh, stlxr, ldaxrb, ldaxrh, ldaxr, stlxp, ldaxp, stlrb, stlrh, stlr, ldarb, ldarh, ldar, clrex.

Usage

Running all Tests

The helper script tools/test.py will build and run every test that is provided with VIXL, in both release and debug mode. It is a useful script for verifying that all of VIXL's dependencies are in place and that VIXL is working as it should.

By default, the tools/test.py script runs a linter to check that the source code conforms with the code style guide, and to detect several common errors that the compiler may not warn about. This is most useful for VIXL developers. The linter has the following dependencies:

  1. Git must be installed, and the VIXL project must be in a valid Git repository, such as one produced using git clone.
  2. cpplint.py, as provided by Google, must be available (and executable) on the PATH.

It is possible to tell tools/test.py to skip the linter stage by passing --nolint. This removes the dependency on cpplint.py and Git. The --nolint option is implied if the VIXL project is a snapshot (with no .git directory).

Additionally, tools/test.py tests code formatting using clang-format-3.6. If you don't have clang-format-3.6, disable the test using the --noclang-format option.

Also note that the tests for the tracing features depend upon external diff and sed tools. If these tools are not available in PATH, these tests will fail.

Getting Started

A short introduction to using VIXL can be found here. Example source code is provided in the examples directory. You can build all the examples with scons examples from the root directory, or use scons --help to get a detailed list of available build targets.

Using VIXL

In addition to getting started and the examples, you can find documentation and guides on various topics that may be helpful here.