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gerrit-public.fairphone.software / platform / external / vixl / 88c46b84df005638546de5e4e965bdcc31352f48 / . / test / a64 / traces / sim-clz-8h-trace-a64.h
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armvixl5289c592015-03-02 13:52:04 +0000[diff] [blame]1// Copyright 2015, ARM Limited
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are met:
6//
7// * Redistributions of source code must retain the above copyright notice,
8// this list of conditions and the following disclaimer.
9// * Redistributions in binary form must reproduce the above copyright notice,
10// this list of conditions and the following disclaimer in the documentation
11// and/or other materials provided with the distribution.
12// * Neither the name of ARM Limited nor the names of its contributors may be
13// used to endorse or promote products derived from this software without
14// specific prior written permission.
15//
16// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
17// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
18// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
19// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
20// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
22// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
23// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26
27
28// ---------------------------------------------------------------------
29// This file is auto generated using tools/generate_simulator_traces.py.
30//
31// PLEASE DO NOT EDIT.
32// ---------------------------------------------------------------------
33
34#ifndef VIXL_SIM_CLZ_8H_TRACE_A64_H_
35#define VIXL_SIM_CLZ_8H_TRACE_A64_H_
36
37const uint16_t kExpected_NEON_clz_8H[] = {
38 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0010,
39 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0010, 0x000f,
40 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0010, 0x000f, 0x000e,
41 0x0000, 0x0000, 0x0000, 0x0000, 0x0010, 0x000f, 0x000e, 0x000b,
42 0x0000, 0x0000, 0x0000, 0x0010, 0x000f, 0x000e, 0x000b, 0x0009,
43 0x0000, 0x0000, 0x0010, 0x000f, 0x000e, 0x000b, 0x0009, 0x0009,
44 0x0000, 0x0010, 0x000f, 0x000e, 0x000b, 0x0009, 0x0009, 0x0009,
45 0x0010, 0x000f, 0x000e, 0x000b, 0x0009, 0x0009, 0x0009, 0x0002,
46 0x000f, 0x000e, 0x000b, 0x0009, 0x0009, 0x0009, 0x0002, 0x0001,
47 0x000e, 0x000b, 0x0009, 0x0009, 0x0009, 0x0002, 0x0001, 0x0001,
48 0x000b, 0x0009, 0x0009, 0x0009, 0x0002, 0x0001, 0x0001, 0x0001,
49 0x0009, 0x0009, 0x0009, 0x0002, 0x0001, 0x0001, 0x0001, 0x0001,
50 0x0009, 0x0009, 0x0002, 0x0001, 0x0001, 0x0001, 0x0001, 0x0000,
51 0x0009, 0x0002, 0x0001, 0x0001, 0x0001, 0x0001, 0x0000, 0x0000,
52 0x0002, 0x0001, 0x0001, 0x0001, 0x0001, 0x0000, 0x0000, 0x0000,
53 0x0001, 0x0001, 0x0001, 0x0001, 0x0000, 0x0000, 0x0000, 0x0000,
54 0x0001, 0x0001, 0x0001, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
55 0x0001, 0x0001, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
56 0x0001, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
57 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
58 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
59 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
60 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
61 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
62};
63const unsigned kExpectedCount_NEON_clz_8H = 24;
64
65#endif // VIXL_SIM_CLZ_8H_TRACE_A64_H_