commit 1af1a7841be9bf3d797f188b716917c80a0aae35
author Chia-I Wu <olv@lunarg.com> Thu Jul 09 10:46:39 2015 +0800
committer Courtney Goeltzenleuchter <courtney@LunarG.com> Fri Jul 17 10:05:17 2015 -0600
tree 409e9a5dfc5f50446f1cb3d708d5ea8ba791c7d3
parent 9e81ebbd16f67780dff31214969fb0cecd4af098

intel: get depth/stencil layout from VkRenderPassCreateInfo

We will not be able to tell RT and DS from VkFramebufferCreateInfo after an
upcoming header change.

icd/intel/cmd_pipeline.c

diff --git a/icd/intel/cmd_pipeline.c b/icd/intel/cmd_pipeline.c
index 6d1b0f5..131a739 100644
--- a/icd/intel/cmd_pipeline.c
+++ b/icd/intel/cmd_pipeline.c
@@ -2036,6 +2036,7 @@
 
 static void emit_ds(struct intel_cmd *cmd)
 {
+    const struct intel_render_pass *rp = cmd->bind.render_pass;
     const struct intel_fb *fb = cmd->bind.fb;
     const struct intel_ds_view *ds = fb->ds;
 
@@ -2049,9 +2050,9 @@
     }
 
     cmd_wa_gen6_pre_ds_flush(cmd);
-    gen6_3DSTATE_DEPTH_BUFFER(cmd, ds, fb->optimal_ds);
-    gen6_3DSTATE_STENCIL_BUFFER(cmd, ds, fb->optimal_ds);
-    gen6_3DSTATE_HIER_DEPTH_BUFFER(cmd, ds, fb->optimal_ds);
+    gen6_3DSTATE_DEPTH_BUFFER(cmd, ds, rp->optimal_ds);
+    gen6_3DSTATE_STENCIL_BUFFER(cmd, ds, rp->optimal_ds);
+    gen6_3DSTATE_HIER_DEPTH_BUFFER(cmd, ds, rp->optimal_ds);
 
     if (cmd_gen(cmd) >= INTEL_GEN(7))
         gen7_3DSTATE_CLEAR_PARAMS(cmd, 0);

icd/intel/fb.c

diff --git a/icd/intel/fb.c b/icd/intel/fb.c
index 30ec8dc..1fd9678 100644
--- a/icd/intel/fb.c
+++ b/icd/intel/fb.c
@@ -97,19 +97,8 @@
         }
 
         fb->ds = ds;
-
-        switch (att->layout) {
-        case VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL:
-        case VK_IMAGE_LAYOUT_DEPTH_STENCIL_READ_ONLY_OPTIMAL:
-            fb->optimal_ds = true;
-            break;
-        default:
-            fb->optimal_ds = false;
-            break;
-        }
     } else {
         fb->ds = NULL;
-        fb->optimal_ds = false;
     }
 
     fb->width = width;
@@ -173,6 +162,16 @@
     rp->depthStencilLayout = info->depthStencilLayout;
     rp->depthStencilFormat = info->depthStencilFormat;
 
+    switch (info->depthStencilLayout) {
+    case VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL:
+    case VK_IMAGE_LAYOUT_DEPTH_STENCIL_READ_ONLY_OPTIMAL:
+        rp->optimal_ds = true;
+        break;
+    default:
+        rp->optimal_ds = false;
+        break;
+    }
+
     /* TODO: MSAA resolves if/when we support MSAA. */
     for (i = 0; i < info->colorAttachmentCount; i++)
         assert(info->pColorStoreOps[i] != VK_ATTACHMENT_STORE_OP_RESOLVE_MSAA);

icd/intel/fb.h

diff --git a/icd/intel/fb.h b/icd/intel/fb.h
index fe1cba4..fa9c1c1 100644
--- a/icd/intel/fb.h
+++ b/icd/intel/fb.h
@@ -36,7 +36,6 @@
     uint32_t rt_count;
 
     const struct intel_ds_view *ds;
-    bool optimal_ds;
 
     uint32_t sample_count;
     uint32_t width;
@@ -62,6 +61,7 @@
     uint32_t stencilLoadClearValue;
     VkImageLayout depthStencilLayout;
     VkFormat depthStencilFormat;
+    bool optimal_ds;
 };
 
 static inline struct intel_fb *intel_fb(VkFramebuffer fb)