commit 2caf749ce60a235035c92eb75132d3e2917766dc
author Chia-I Wu <olvaffe@gmail.com> Sun Aug 31 12:28:38 2014 +0800
committer Chia-I Wu <olvaffe@gmail.com> Sun Aug 31 12:30:15 2014 +0800
tree c6dd50af86be5697bbdc0b18c069b587c995f574
parent c137a159ebfae7a276c2307f0bb5bed8bb08f2ad

intel: limit INTEL_RELOC_GGTT to GEN6

Only need it on GEN6.

icd/intel/cmd_pipeline.c

diff --git a/icd/intel/cmd_pipeline.c b/icd/intel/cmd_pipeline.c
index 99489b2..6850081 100644
--- a/icd/intel/cmd_pipeline.c
+++ b/icd/intel/cmd_pipeline.c
@@ -96,6 +96,7 @@
    const uint8_t cmd_len = 5;
    const uint32_t dw0 = GEN6_RENDER_CMD(3D, PIPE_CONTROL) |
                         (cmd_len - 2);
+   uint32_t reloc_flags = INTEL_RELOC_WRITE;
 
    CMD_ASSERT(cmd, 6, 7.5);
 
@@ -162,18 +163,18 @@
     * The kernel will add the mapping automatically (when write domain is
     * INTEL_DOMAIN_INSTRUCTION).
     */
-   if (cmd_gen(cmd) == INTEL_GEN(6) && bo)
+   if (cmd_gen(cmd) == INTEL_GEN(6) && bo) {
       bo_offset |= GEN6_PIPE_CONTROL_DW2_USE_GGTT;
+      reloc_flags |= INTEL_RELOC_GGTT;
+   }
 
    cmd_batch_reserve_reloc(cmd, cmd_len, (bool) bo);
    cmd_batch_write(cmd, dw0);
    cmd_batch_write(cmd, dw1);
-   if (bo) {
-       cmd_batch_reloc(cmd, bo_offset, bo, INTEL_RELOC_GGTT |
-                                           INTEL_RELOC_WRITE);
-   } else {
+   if (bo)
+       cmd_batch_reloc(cmd, bo_offset, bo, reloc_flags);
+   else
        cmd_batch_write(cmd, 0);
-   }
    cmd_batch_write(cmd, 0);
    cmd_batch_write(cmd, 0);
 }